Inventor · disambiguated record
Antony John Penton
Also filed as: PENTON ANTONY JOHN
39 granted patents·4 pending applications·69 citations·filing 2004–2023
96Inventor score
Files withADVANCED RISC MACH LTD34PENTON ANTONY JOHN5CRASKE SIMON JOHN2PATHIRANE CHILODA ASHAN SENERATH1VASEKIN VLADIMIR1
Top patents by PatentIndex Score
43 records- 0186US8051323B2Auxiliary circuit structure in a split-lock dual processor systemADVANCED RISC MACH LTD·Filed 2010·Granted Nov 1, 2011·10 cites·19 claims
- 0283US8356119B2Performance by reducing transaction request ordering requirementsADVANCED RISC MACH LTD·Filed 2010·Granted Jan 15, 2013·10 cites·20 claims
- 0380US9977679B2Apparatus and method for suspending execution of a thread in response to a hint instructionADVANCED RISC MACH LTD·Filed 2015·Granted May 22, 2018·3 cites·15 claims
- 0478US8661232B2Register state saving and restoringPENTON ANTONY JOHN·Filed 2010·Granted Feb 25, 2014·6 cites·35 claims
- 0577US8484508B2Data processing apparatus and method for providing fault tolerance when executing a sequence of data processing operationsPENTON ANTONY JOHN·Filed 2010·Granted Jul 9, 2013·5 cites·13 claims
- 0676US10303566B2Apparatus and method for checking output data during redundant execution of instructionsADVANCED RISC MACH LTD·Filed 2017·Granted May 28, 2019·2 cites·20 claims
- 0774US8190973B2Apparatus and method for error correction of data values in a storage devicePENTON ANTONY JOHN·Filed 2007·Granted May 29, 2012·7 cites·15 claims
- 0870US8374098B2Check data encoding using parallel lane encodersADVANCED RISC MACH LTD·Filed 2009·Granted Feb 12, 2013·4 cites·26 claims
- 0967US9836403B2Dynamic cache allocation policy adaptation in a data processing apparatusADVANCED RISC MACH LTD·Filed 2015·Granted Dec 5, 2017·2 cites·19 claims
- 1066US8499017B2Apparatus and method for performing fused multiply add floating point operationPENTON ANTONY JOHN·Filed 2009·Granted Jul 30, 2013·3 cites·32 claims
- 1165US10705587B2Mode switching in dependence upon a number of active threadsADVANCED RISC MACH LTD·Filed 2016·Granted Jul 7, 2020·1 cites·17 claims
- 1264US7489752B2Synchronisation of signals between asynchronous logicADVANCED RISC MACH LTD·Filed 2005·Granted Feb 10, 2009·3 cites·11 claims
- 1363US12277028B2Error correction codeADVANCED RISC MACH LTD·Filed 2023·Granted Apr 15, 2025·0 cites·18 claims
- 1462US11579879B2Processing pipeline with first and second processing modes having different performance or energy consumption characteristicsADVANCED RISC MACH LTD·Filed 2021·Granted Feb 14, 2023·0 cites·14 claims
- 1560US11579889B2Programmable instruction buffering for accumulating a burst of instructionsADVANCED RISC MACH LTD·Filed 2020·Granted Feb 14, 2023·0 cites·18 claims
- 1660US11055440B2Handling access attributes for data accessesADVANCED RISC MACH LTD·Filed 2019·Granted Jul 6, 2021·0 cites·16 claims
- 1760US8977820B2Handling of hard errors in a cache of a data processing apparatusPENTON ANTONY JOHN·Filed 2007·Granted Mar 10, 2015·2 cites·16 claims
- 1859US11074080B2Apparatus and branch prediction circuitry having first and second branch prediction schemes, and methodADVANCED RISC MACH LTD·Filed 2020·Granted Jul 27, 2021·0 cites·9 claims
- 1958US8621336B2Error correction in a set associative storage deviceCRASKE SIMON JOHN·Filed 2008·Granted Dec 31, 2013·1 cites·15 claims
- 2056US10866810B2Programmable instruction buffering of a burst of instructions including a pending data write to a given memory address and a subsequent data read of said given memory addressADVANCED RISC MACH LTD·Filed 2018·Granted Dec 15, 2020·0 cites·18 claims
- 2155US12292834B2Cache prefetchingADVANCED RISC MACH LTD·Filed 2023·Granted May 6, 2025·0 cites·18 claims
- 2255US10354092B2Handling access attributes for data accessesADVANCED RISC MACH LTD·Filed 2014·Granted Jul 16, 2019·0 cites·14 claims
- 2355US8954715B2Thread selection for multithreaded processingVASEKIN VLADIMIR·Filed 2012·Granted Feb 10, 2015·1 cites·18 claims
- 2455US7085874B2Synchronous/asynchronous bridge circuit for improved transfer of data between two circuitsADVANCED RISC MACH LTD·Filed 2004·Granted Aug 1, 2006·8 cites·20 claims
- 2554US11275607B2Improving the responsiveness of an apparatus to certain interruptsADVANCED RISC MACH LTD·Filed 2020·Granted Mar 15, 2022·0 cites·22 claims
- 2654US2025045154A1Address digestADVANCED RISC MACH LTD·Filed 2023·Application pending·0 cites
- 2753US10817369B2Apparatus and method for increasing resilience to faultsADVANCED RISC MACH LTD·Filed 2018·Granted Oct 27, 2020·0 cites·19 claims
- 2853US8108730B2Debugging a multiprocessor system that switches between a locked mode and a split modePATHIRANE CHILODA ASHAN SENERATH·Filed 2010·Granted Jan 31, 2012·1 cites·19 claims
- 2951US10963250B2Selectively suppressing time intensive instructions based on a control valueADVANCED RISC MACH LTD·Filed 2014·Granted Mar 30, 2021·0 cites·24 claims
- 3050US9886276B2System register accessADVANCED RISC MACH LTD·Filed 2014·Granted Feb 6, 2018·0 cites·19 claims
- 3150US2016357561A1Apparatus having processing pipeline with first and second execution circuitry, and methodADVANCED RISC MACH LTD·Filed 2016·Application pending·0 cites
- 3249US2018150297A1Processing pipeline with first and second processing modes having different performance or energy consumption characteristicsADVANCED RISC MACH LTD·Filed 2016·Application pending·0 cites
- 3347US10997076B2Asymmetric coherency protocol for first and second processing circuitry having different levels of fault protection or fault detectionADVANCED RISC MACH LTD·Filed 2016·Granted May 4, 2021·0 cites·18 claims
- 3447US10289332B2Apparatus and method for increasing resilience to faultsADVANCED RISC MACH LTD·Filed 2017·Granted May 14, 2019·0 cites·20 claims
- 3545US8756377B2Area and power efficient data coherency maintenanceCRASKE SIMON JOHN·Filed 2010·Granted Jun 17, 2014·0 cites·22 claims
- 3644US10620953B2Instruction prefetch halting upon predecoding predetermined instruction typesADVANCED RISC MACH LTD·Filed 2017·Granted Apr 14, 2020·0 cites·11 claims
- 3743US12009041B2Apparatus and method for detecting errors in a memory deviceADVANCED RISC MACH LTD·Filed 2022·Granted Jun 11, 2024·0 cites·18 claims
- 3843US9952871B2Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitryADVANCED RISC MACH LTD·Filed 2015·Granted Apr 24, 2018·0 cites·18 claims
- 3942US10402203B2Determining a predicted behaviour for processing of instructionsADVANCED RISC MACH LTD·Filed 2016·Granted Sep 3, 2019·0 cites·19 claims
- 4042US10296349B2Allocating a register to an instruction using register index informationADVANCED RISC MACH LTD·Filed 2016·Granted May 21, 2019·0 cites·18 claims
- 4141US11194577B2Instruction issue according to in-order or out-of-order execution modesADVANCED RISC MACH LTD·Filed 2016·Granted Dec 7, 2021·0 cites·23 claims
- 4240US2011179255A1Data processing reset operationsADVANCED RISC MACH LTD·Filed 2010·Application pending·0 cites
- 4336US9940137B2Processor exception handling using a branch target cacheADVANCED RISC MACH LTD·Filed 2016·Granted Apr 10, 2018·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →