Processing pipeline with first and second processing modes having different performance or energy consumption characteristics

Abstract

An apparatus ( 2 ) has a processing pipeline ( 4 ) supporting at least a first processing mode and a second processing mode with different energy consumption or performance characteristics. A storage structure ( 22, 30, 36, 50, 40, 64, 44 ) is accessible in both the first and second processing modes. When the second processing mode is selected, control circuitry ( 70 ) triggers a subset ( 102 ) of the entries of the storage structure to be placed in a power saving state.

1 . An apparatus comprising:
 a processing pipeline to process instructions, the processing pipeline having at least a first processing mode and a second processing mode with different performance or energy consumption characteristics;   a storage structure accessible to the processing pipeline in both the first processing mode and the second processing mode, the storage structure comprising a plurality of entries; and   control circuitry to select one of the first processing mode and the second processing mode of the processing pipeline, and to trigger a subset of the entries of the storage structure to be placed in a power saving state when the second processing mode is selected.   
     
     
         2 . The apparatus according to  claim 1 , wherein in the first processing mode, the processing pipeline has a greater maximum throughput of instructions than in the second processing mode. 
     
     
         3 . The apparatus according to  claim 1 , wherein on switching the processing circuitry from the first processing mode to the second processing mode, the control circuitry is configured to disable further allocation of information to said subset of entries. 
     
     
         4 . The apparatus according to  claim 3 , wherein the control circuitry is configured to prevent the processing pipeline accessing information in said subset of entries when further allocation of information to said subset of entries is disabled. 
     
     
         5 . The apparatus according to  claim 3 , wherein the control circuitry is configured to allow the processing pipeline to continue to access information within at least some of said subset of entries for a period after disabling said further allocation of information to said subset of entries. 
     
     
         6 . The apparatus according to  claim 5 , wherein the control circuitry is configured to trigger one of said subset of entries to be placed in the power saving state in response to an indication that the processing pipeline no longer requires said one of said subset of entries. 
     
     
         7 . The apparatus according to  claim 5 , wherein the processing pipeline is configured to process instructions in the second processing mode during said period when the processing pipeline is allowed to continue to access information in said subset of entries. 
     
     
         8 . The apparatus according to  claim 1 , wherein on switching the processing pipeline from the second processing mode to the first processing mode, the control circuitry is configured to enable further allocation of information to said subset of entries. 
     
     
         9 . The apparatus according to  claim 1 , wherein the storage structure is configured to store architectural state data for the processing pipeline, indications of pending instructions being processed by the processing pipeline or control data for controlling how instructions are processed by the processing pipeline. 
     
     
         10 . The apparatus according to  claim 1 , wherein the storage structure comprises a translation lookaside buffer to store address translation data for translating addresses. 
     
     
         11 . The apparatus according to  claim 1 , wherein the storage structure comprises a branch prediction table to store branch prediction data for predicting outcomes of branch instructions. 
     
     
         12 . The apparatus according to  claim 1 , wherein the storage structure comprises an instruction queue to queue pending instructions to be processed by the processing pipeline. 
     
     
         13 . The apparatus according to  claim 12 , wherein the instruction queue comprises a decode queue to queue pending instructions to be decoded. 
     
     
         14 . The apparatus according to  claim 12 , wherein the instruction queue comprises an issue queue to queue pending instructions to be issued for execution. 
     
     
         15 . The apparatus according to  claim 1 , wherein the processing pipeline supports out-of-order execution of instructions in both the first processing mode and the second processing mode, and the storage structure comprises a reorder buffer to store information for tracking completion of execution of instructions by the processing pipeline. 
     
     
         16 . The apparatus according to  claim 1 , wherein the storage structure comprises a load/store queue to queue pending load operations for loading data from a cache or memory or pending store operations for storing data to the cache or the memory. 
     
     
         17 . The apparatus according to  claim 1 , wherein the storage structure comprises a buffer to store data read from a storage device prior to the read data being accessed by the processing pipeline or stored in at least one cache. 
     
     
         18 . The apparatus according to  claim 1 , wherein the storage structure comprises a plurality of physical registers to store data values accessible to the processing pipeline in response to instructions. 
     
     
         19 . The apparatus according to  claim 18 , comprising register renaming circuitry to map architectural register specifiers specified by instructions to corresponding physical registers at least in the first processing mode. 
     
     
         20 . The apparatus according to  claim 19 , wherein on switching the processing pipeline from the first processing mode to the second processing mode, the register renaming circuitry is configured to disable further allocation of a subset of the physical registers to architectural register specifiers. 
     
     
         21 . The apparatus according to  claim 18 , wherein, on switching the processing pipeline from the first processing mode to the second processing mode, the register renaming circuitry is configured to remap one or more architectural register specifiers currently mapped to said subset of physical registers to alternate physical registers other than said subset of physical registers. 
     
     
         22 . The apparatus according to  claim 21 , wherein the register renaming circuitry is configured to remap a given architectural register specifier currently mapped to one of said subset of physical registers to an alternate physical register in response to an instruction to be processed by the processing pipeline which specifies the given architectural register specifier as a destination register. 
     
     
         23 . The apparatus according to any  claim 21 , wherein the register renaming circuitry is configured to remap a given architectural register specifier currently mapped to one of said subset of physical registers to an alternate physical register, and to trigger an additional instruction to be processed by the processing pipeline to control the processing pipeline to move a data value from one of said subset of the physical registers to said alternate physical register. 
     
     
         24 . The apparatus according to  claim 19 , comprising a rename table to identify current mappings between architectural register specifiers and physical registers;
 wherein on switching the processing pipeline from the first processing mode to the second processing mode, the register rename circuitry is configured to remap each architectural register specifier to a predetermined physical register, and the control circuitry is configured to trigger the rename table and the physical registers other than said predetermined group of physical registers to be placed in a power saving state.   
     
     
         25 . (canceled) 
     
     
         26 . A method comprising:
 selecting one of at least a first processing mode and a second processing mode of a processing pipeline for processing instructions, the first processing mode and the second processing mode having different performance or energy consumption characteristics, the processing pipeline having access to a storage structure in both the first processing mode and the second processing mode, the storage structure having a plurality of entries; and   when the second processing mode is selected, placing a subset of the entries of the storage structure in a power saving state.