Inventor · disambiguated record
Ian Michael Caulfield
Also filed as: CAULFIELD IAN MICHAEL
31 granted patents·8 pending applications·66 citations·filing 2009–2022
94Inventor score
Top patents by PatentIndex Score
39 records- 0197US10394716B1Apparatus and method for controlling allocation of data into a cache storageADVANCED RISC MACH LTD·Filed 2018·Granted Aug 27, 2019·41 cites·19 claims
- 0290US10579389B2Fusion of instructions by delaying handling of a partial subset of a fusible group of instructionsADVANCED RISC MACH LTD·Filed 2015·Granted Mar 3, 2020·9 cites·18 claims
- 0380US10725923B1Cache access detection and predictionADVANCED RISC MACH LTD·Filed 2019·Granted Jul 28, 2020·3 cites·20 claims
- 0480US9977679B2Apparatus and method for suspending execution of a thread in response to a hint instructionADVANCED RISC MACH LTD·Filed 2015·Granted May 22, 2018·3 cites·15 claims
- 0578US11340901B2Apparatus and method for controlling allocation of instructions into an instruction cache storageADVANCED RISC MACH LTD·Filed 2019·Granted May 24, 2022·2 cites·13 claims
- 0667US9330035B2Method and apparatus for interrupt handlingADVANCED RISC MACH LTD·Filed 2013·Granted May 3, 2016·2 cites·20 claims
- 0766US8499017B2Apparatus and method for performing fused multiply add floating point operationPENTON ANTONY JOHN·Filed 2009·Granted Jul 30, 2013·3 cites·32 claims
- 0865US10705587B2Mode switching in dependence upon a number of active threadsADVANCED RISC MACH LTD·Filed 2016·Granted Jul 7, 2020·1 cites·17 claims
- 0964US10521368B2Arbitration of requests requiring a variable number of resourcesADVANCED RISC MACH LTD·Filed 2015·Granted Dec 31, 2019·1 cites·16 claims
- 1063US10564973B2Apparatus and method for sharing branch information storage entries between threads that share an address translation regimeADVANCED RISC MACH LTD·Filed 2015·Granted Feb 18, 2020·1 cites·16 claims
- 1163US2022291923A1Register-based matrix multiplicationADVANCED RISC MACH LTD·Filed 2022·Application pending·0 cites
- 1262US11579879B2Processing pipeline with first and second processing modes having different performance or energy consumption characteristicsADVANCED RISC MACH LTD·Filed 2021·Granted Feb 14, 2023·0 cites·14 claims
- 1359US11074080B2Apparatus and branch prediction circuitry having first and second branch prediction schemes, and methodADVANCED RISC MACH LTD·Filed 2020·Granted Jul 27, 2021·0 cites·9 claims
- 1456US12182261B2Controlling use of data determined by a resolve-pending speculative operationADVANCED RISC MACH LTD·Filed 2019·Granted Dec 31, 2024·0 cites·19 claims
- 1555US10552160B2Handling stalling event for multiple thread pipeline, and triggering action based on information access delayADVANCED RISC MACH LTD·Filed 2018·Granted Feb 4, 2020·0 cites·13 claims
- 1654US11288066B2Register-based matrix multiplication with multiple matrices per registerADVANCED RISC MACH LTD·Filed 2018·Granted Mar 29, 2022·0 cites·17 claims
- 1753US11526615B2Speculative side-channel hint instructionADVANCED RISC MACH LTD·Filed 2019·Granted Dec 13, 2022·0 cites·17 claims
- 1852US12050805B2Control of bulk memory instructionsADVANCED RISC MACH LTD·Filed 2022·Granted Jul 30, 2024·0 cites·20 claims
- 1952US11803388B2Apparatus and method for predicting source operand values and optimized processing of instructionsADVANCED RISC MACH LTD·Filed 2019·Granted Oct 31, 2023·0 cites·20 claims
- 2052US11397584B2Tracking speculative data cachingADVANCED RISC MACH LTD·Filed 2019·Granted Jul 26, 2022·0 cites·11 claims
- 2152US11392383B2Apparatus and method for prefetching data itemsADVANCED RISC MACH LTD·Filed 2019·Granted Jul 19, 2022·0 cites·13 claims
- 2252US11126714B2Encoding of input to storage circuitryADVANCED RISC MACH LTD·Filed 2018·Granted Sep 21, 2021·0 cites·29 claims
- 2350US2016357561A1Apparatus having processing pipeline with first and second execution circuitry, and methodADVANCED RISC MACH LTD·Filed 2016·Application pending·0 cites
- 2449US10592517B2Ranking itemsADVANCED RISC MACH LTD·Filed 2017·Granted Mar 17, 2020·0 cites·20 claims
- 2549US2024386094A1Apparatus and method for pointer authenticationADVANCED RISC MACH LTD·Filed 2022·Application pending·0 cites
- 2649US2018150297A1Processing pipeline with first and second processing modes having different performance or energy consumption characteristicsADVANCED RISC MACH LTD·Filed 2016·Application pending·0 cites
- 2748US11263133B2Cache control in presence of speculative read operationsADVANCED RISC MACH LTD·Filed 2019·Granted Mar 1, 2022·0 cites·14 claims
- 2848US2017139716A1Handling stalling event for multiple thread pipeline, and triggering action based on information access delayADVANCED RISC MACH LTD·Filed 2015·Application pending·0 cites
- 2947US10310735B2Data storageADVANCED RISC MACH LTD·Filed 2017·Granted Jun 4, 2019·0 cites·13 claims
- 3046US10140093B2Apparatus and method for estimating a shift amount when performing floating-point subtractionADVANCED RISC MACH LTD·Filed 2017·Granted Nov 27, 2018·0 cites·19 claims
- 3146US9213547B2Processor and method for processing instructions using at least one processing pipelineADVANCED RISC MACH LTD·Filed 2013·Granted Dec 15, 2015·0 cites·18 claims
- 3246US2015261542A1Data processing apparatus and method for performing data processing operation with a conditional processing stepADVANCED RISC MACH LTD·Filed 2014·Application pending·0 cites
- 3346US2014365751A1Operand generation in at least one processing pipelineADVANCED RISC MACH LTD·Filed 2014·Application pending·0 cites
- 3445US10846092B2Execution of micro-operationsADVANCED RISC MACH LTD·Filed 2016·Granted Nov 24, 2020·0 cites·17 claims
- 3545US2020410088A1Micro-instruction cache annotations to indicate speculative side-channel risk condition for read instructionsADVANCED RISC MACH LTD·Filed 2019·Application pending·0 cites
- 3643US9952871B2Controlling execution of instructions for a processing pipeline having first out-of order execution circuitry and second execution circuitryADVANCED RISC MACH LTD·Filed 2015·Granted Apr 24, 2018·0 cites·18 claims
- 3742US10402203B2Determining a predicted behaviour for processing of instructionsADVANCED RISC MACH LTD·Filed 2016·Granted Sep 3, 2019·0 cites·19 claims
- 3841US10095518B2Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instructionADVANCED RISC MACH LTD·Filed 2015·Granted Oct 9, 2018·0 cites·18 claims
- 3938US11429393B2Apparatus and method for supporting out-of-order program execution of instructionsADVANCED RISC MACH LTD·Filed 2015·Granted Aug 30, 2022·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →