Inventor · disambiguated record
Anthony M. Petro
Also filed as: PETRO ANTHONY M
27 granted patents·426 citations·filing 1997–2000
97Inventor score
Top patents by PatentIndex Score
27 records- 0184US6066965AMethod and apparatus for a N-nary logic circuit using 1 of 4 signalsEVSX INC·Filed 1998·Granted May 23, 2000·48 cites·16 claims
- 0280US6107835AMethod and apparatus for a logic circuit with constant power consumptionINTRINSITY INC·Filed 1998·Granted Aug 22, 2000·36 cites·20 claims
- 0380US6069497AMethod and apparatus for a N-nary logic circuit using 1 of N signalsEVSX INC·Filed 1998·Granted May 30, 2000·40 cites·24 claims
- 0477US6118304AMethod and apparatus for logic synchronizationINTRINSITY INC·Filed 1998·Granted Sep 12, 2000·33 cites·25 claims
- 0573US6275841B11-of-4 multiplierINTRINSITY INC·Filed 1998·Granted Aug 14, 2001·33 cites·24 claims
- 0669US6288589B1Method and apparatus for generating clock signalsINTRINSITY INC·Filed 1998·Granted Sep 11, 2001·29 cites·20 claims
- 0765US6301600B1Method and apparatus for dynamic partitionable saturating adder/subtractorINTRINSITY INC·Filed 1998·Granted Oct 9, 2001·46 cites·11 claims
- 0865US6268746B1Method and apparatus for logic synchronizationINTRINSITY INC·Filed 2000·Granted Jul 31, 2001·10 cites·16 claims
- 0965US6032252AApparatus and method for efficient loop control in a superscalar microprocessorADVANCED MICRO DEVICES INC·Filed 1997·Granted Feb 29, 2000·46 cites·17 claims
- 1049US6911846B1Method and apparatus for a 1 of N signalINTRINSITY INC·Filed 1998·Granted Jun 28, 2005·11 cites·16 claims
- 1145US6334183B1Method and apparatus for handling partial register accessesINTRINSITY INC·Filed 1998·Granted Dec 25, 2001·17 cites·36 claims
- 1242US6324239B1Method and apparatus for a 1 of 4 shifterINTRINSITY INC·Filed 1998·Granted Nov 27, 2001·6 cites·12 claims
- 1341US6233707B1Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate's clockINTRINSITY INC·Filed 1998·Granted May 15, 2001·12 cites·28 claims
- 1438US6571378B1Method and apparatus for a N-NARY logic circuit using capacitance isolationINTRINSITY INC·Filed 2000·Granted May 27, 2003·1 cites·15 claims
- 1536US6334136B1Dynamic 3-level partial result merge adderINTRINSITY INC·Filed 1998·Granted Dec 25, 2001·8 cites·20 claims
- 1635US6347327B1Method and apparatus for N-nary incrementorINTRINSITY INC·Filed 1998·Granted Feb 12, 2002·7 cites·6 claims
- 1735US6219687B1Method and apparatus for an N-nary Sum/HPG gateINTRINSITY INC·Filed 1998·Granted Apr 17, 2001·3 cites·21 claims
- 1835US6216147B1Method and apparatus for an N-nary magnitude comparatorINTRINSITY INC·Filed 1998·Granted Apr 10, 2001·7 cites·8 claims
- 1934US6269387B1Method and apparatus for 3-stage 32-bit adder/subtractorINTRINSITY INC·Filed 1998·Granted Jul 31, 2001·6 cites·28 claims
- 2034US6252425B1Method and apparatus for an N-NARY logic circuitINTRINSITY INC·Filed 1999·Granted Jun 26, 2001·5 cites·28 claims
- 2133US6223199B1Method and apparatus for an N-NARY HPG gateINTRINSITY INC·Filed 1998·Granted Apr 24, 2001·5 cites·16 claims
- 2233US6216146B1Method and apparatus for an N-nary adder gateINTRINSITY INC·Filed 1998·Granted Apr 10, 2001·2 cites·16 claims
- 2333US6124735AMethod and apparatus for a N-nary logic circuit using capacitance isolationINTRINSITY INC·Filed 1998·Granted Sep 26, 2000·4 cites·23 claims
- 2432US6301597B1Method and apparatus for saturation in an N-NARY adder/subtractorINTRINSITY INC·Filed 1998·Granted Oct 9, 2001·4 cites·28 claims
- 2532US6272514B1Method and apparatus for interruption of carry propagation on partition boundariesINTRINSITY INC·Filed 1998·Granted Aug 7, 2001·3 cites·24 claims
- 2632US6219686B1Method and apparatus for an N-NARY sum/HPG adder/subtractor gateINTRINSITY INC·Filed 1998·Granted Apr 17, 2001·4 cites·38 claims
- 2730US6154120AMethod and apparatus for an N-nary equality comparatorEVSX INC·Filed 1998·Granted Nov 28, 2000·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →