Inventor · disambiguated record
Andrei Sergeevich Terechko
Also filed as: TERECHKO ANDREI · TERECHKO ANDREI S · TERECHKO ANDREI SERGEEVICH
11 granted patents·11 pending applications·156 citations·filing 2003–2024
90Inventor score
Top patents by PatentIndex Score
22 records- 0190US10554521B1Health monitoring of wireless connections among vehiclesNXP BV·Filed 2018·Granted Feb 4, 2020·20 cites·20 claims
- 0288US7500126B2Arrangement and method for controlling power modes of hardware resourcesNXP BV·Filed 2003·Granted Mar 3, 2009·46 cites·14 claims
- 0387US7539879B2Register file gating to reduce microprocessor power dissipationNXP BV·Filed 2003·Granted May 26, 2009·54 cites·21 claims
- 0482US10628275B2Runtime software-based self-test with mutual inter-core checkingNXP BV·Filed 2018·Granted Apr 21, 2020·6 cites·20 claims
- 0578US11142212B2Safety-aware comparator for redundant subsystems in autonomous vehiclesNXP BV·Filed 2019·Granted Oct 12, 2021·3 cites·23 claims
- 0677US8265160B2Parallel three-dimensional recursive search (3DRS) meandering algorithmAL-KADI GHIATH·Filed 2009·Granted Sep 11, 2012·9 cites·20 claims
- 0776US8732408B2Circuit and method with cache coherence stress controlKARLAPALEM SAINATH·Filed 2008·Granted May 20, 2014·11 cites·32 claims
- 0873US8181054B2Arrangement and method for controlling power modes of hardware resourcesTERECHKO ANDREI·Filed 2011·Granted May 15, 2012·4 cites·17 claims
- 0961US8578104B2Multiprocessor system with mixed software hardware controlled cache managementHOOGERBRUGGE JAN·Filed 2009·Granted Nov 5, 2013·2 cites·15 claims
- 1057US8607246B2Multiprocessor circuit using run-time task schedulingAL-KADI GHIATH·Filed 2009·Granted Dec 10, 2013·1 cites·10 claims
- 1154US11909851B2Coalescing interrupts based on fragment information in packets and a network controller for coalescingNXP BV·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 1253US2025360923A1Advisory vehicle speed assistanceNXP BV·Filed 2024·Application pending·0 cites
- 1349US2011082981A1Multiprocessing circuit with cache circuits that allow writing to not previously loaded cache linesNXP BV·Filed 2009·Application pending·0 cites
- 1449US2011099337A1Processing circuit with cache circuit and detection of runs of updated addresses in cache linesNXP BV·Filed 2009·Application pending·0 cites
- 1549US2024416962A1Cross-Channel Safety Analysis of Redundant MPC-Based Vehicle Controllers in Autonomous SystemsNXP USA INC·Filed 2023·Application pending·0 cites
- 1649US2009125742A1Arrangement and method for controlling power modes of hardware resourcesTERECHKO ANDREI·Filed 2009·Application pending·0 cites
- 1746US2011004881A1Look-ahead task managementNXP BV·Filed 2009·Application pending·0 cites
- 1844US2006200646A1Data processing system with clustered ilp processorKONINKL PHILIPS ELECTRONICS NV·Filed 2004·Application pending·0 cites
- 1944US2024149817A1Animal Detection And Repelling For Automated Driving SystemsNXP BV·Filed 2022·Application pending·0 cites
- 2042US2006095710A1Clustered ilp processor and a method for accessing a bus in a clustered ilp processorKONINKL PHILIPS ELECTRONICS NV·Filed 2003·Application pending·0 cites
- 2142US2006101233A1Clustered instruction level parallelism processorKONINKL PHILIPS ELECTRONICS NV·Filed 2003·Application pending·0 cites
- 2234US2009063780A1Data processing system and method for monitoring the cache coherence of processing unitsKONINKL PHILIPS ELECTRONICS NV·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →