Arrangement and method for controlling power modes of hardware resources

Abstract

A circuit arrangement and method of executing program code which utilize power control instructions capable of dynamically controlling power dissipation of multiple hardware resources during execution of a program by a processor. The processor configured to process such power control instructions and to maintain the power modes of the multiple hardware resources to that specified in an earlier-processed power control instruction, such that subsequently-processed instructions will be processed while the power modes of the multiple hardware resources are set to that specified by the earlier-processed power control instruction.

1 . A circuit arrangement, comprising:
 a plurality of hardware resources, wherein each hardware resource has a power mode configurable between at least first and second power consumption states; and   a processor coupled to the plurality of hardware resources, the processor configured to process program code that includes at least one power control instruction that includes an operand having power control information disposed therein, wherein the processor is configured to process the power control instruction by selectively setting power modes of at least two hardware resources among the plurality of hardware resources based upon the power control information disposed in the power control instruction, and wherein the processor is further configured to maintain the power modes of the at least two hardware resources to that specified in the power control instruction while processing at least one subsequent instruction in the program code.   
   
   
       2 . The circuit arrangement of  claim 1 , wherein the power control instruction includes an opcode that uniquely identifies the power control instruction. 
   
   
       3 . The circuit arrangement of  claim 1 , wherein each hardware resource is selected from the group consisting of a register file, a register bank, a register, a cache, a bus interface unit, a bus, a functional unit, a functional block and an instruction decoder. 
   
   
       4 . The circuit arrangement of  claim 1 , wherein the processor is configured to process explicitly parallel instructions, and wherein the power control instruction comprises an operation among a plurality of operations in an explicitly parallel instruction. 
   
   
       5 . The circuit arrangement of  claim 4 , wherein the processor is selected from the group consisting of a VLIW processor and an EPIC processor. 
   
   
       6 . The circuit arrangement of  claim 1 , wherein the processor comprises a superscalar processor. 
   
   
       7 . The circuit arrangement of  claim 1 , wherein the processor is configured to assign a side effect to the power control instruction to limit run-time speculation thereof. 
   
   
       8 . The circuit arrangement of  claim 1 , wherein the plurality of hardware resources are disposed in the processor. 
   
   
       9 . The circuit arrangement of  claim 1 , wherein at least one hardware resource is disposed outside of the processor but on the same integrated circuit as the processor. 
   
   
       10 . The circuit arrangement of  claim 1 , wherein at least one hardware resource is disposed on a separate integrated circuit from the processor. 
   
   
       11 . An integrated circuit comprising the circuit arrangement of  claim 1 . 
   
   
       12 . The circuit arrangement of  claim 1 , wherein the processor is further configured to set the power modes of the at least two hardware resources based on stored power modes state information for the plurality of hardware resources. 
   
   
       13 . A method of executing program code on a processor coupled to a plurality of hardware resources, each having a power mode configurable between at least first and second power consumption states, the method comprising:
 processing a power control instruction from the program code by selectively setting power modes of at least two hardware resources among the plurality of hardware resources based upon power control information disposed in an operand of the power control instruction; and   processing at least one subsequent instruction in the program code while the power modes of the at least two hardware resources are set to that specified by the power control information of the power control instruction.   
   
   
       14 . The method of  claim 13 , wherein the power control instruction further includes an opcode that uniquely identifies the power control instruction. 
   
   
       15 . The method of  claim 13 , wherein each hardware resource is selected from the group consisting of a register file, a register bank, a register, a cache, a bus interface unit, a bus, a functional unit, a functional block and an instruction decoder. 
   
   
       16 . The method of  claim 13 , wherein the processor is configured to process explicitly parallel instructions, and wherein the power control instruction comprises an operation among a plurality of operations in an explicitly parallel instruction. 
   
   
       17 . The method of  claim 13 , further comprising setting the power modes of the at least two hardware resources based on stored power modes state information for the plurality of hardware resources.