Inventor · disambiguated record
Andrew Waterman
Also filed as: Waterman Andrew
15 granted patents·8 pending applications·2 citations·filing 2018–2025
85Inventor score
Files withSIFIVE INC23
Top patents by PatentIndex Score
23 records- 0180US11861365B2Macro-op fusionSIFIVE INC·Filed 2021·Granted Jan 2, 2024·1 cites·20 claims
- 0280US2025383877A1Fusion with destructive instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 0376US2025335367A1Logging guest physical address for memory access faultsSIFIVE INC·Filed 2025·Application pending·0 cites
- 0474US12487829B2Macro-op fusion for pipelined architecturesSIFIVE INC·Filed 2024·Granted Dec 2, 2025·0 cites·20 claims
- 0571US12417103B2Fusion with destructive instructionsSIFIVE INC·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 0670US10996952B2Macro-op fusionSIFIVE INC·Filed 2018·Granted May 4, 2021·1 cites·39 claims
- 0767US2025173277A1Memory protection for gather-scatter operationsSIFIVE INC·Filed 2025·Application pending·0 cites
- 0866US12367154B2Logging guest physical address for memory access faultsSIFIVE INC·Filed 2022·Granted Jul 22, 2025·0 cites·19 claims
- 0966US11797308B2Fetch stage handling of indirect jumps in a processor pipelineSIFIVE INC·Filed 2022·Granted Oct 24, 2023·0 cites·20 claims
- 1063US12253959B2Memory protection for gather-scatter operationsSIFIVE INC·Filed 2021·Granted Mar 18, 2025·0 cites·15 claims
- 1163US2024329928A1Quad narrowing operationSIFIVE INC·Filed 2024·Application pending·0 cites
- 1261US12468540B2Technologies for prediction-based register renamingSIFIVE INC·Filed 2021·Granted Nov 11, 2025·0 cites·12 claims
- 1361US12086067B2Load-store pipeline selection for vectorsSIFIVE INC·Filed 2023·Granted Sep 10, 2024·0 cites·22 claims
- 1460US11687342B2Way predictor and enable logic for instruction tightly-coupled memory and instruction cacheSIFIVE INC·Filed 2019·Granted Jun 27, 2023·0 cites·20 claims
- 1558US11301251B2Fetch stage handling of indirect jumps in a processor pipelineSIFIVE INC·Filed 2020·Granted Apr 12, 2022·0 cites·20 claims
- 1658US11048515B2Way predictor and enable logic for instruction tightly-coupled memory and instruction cacheSIFIVE INC·Filed 2019·Granted Jun 29, 2021·0 cites·8 claims
- 1752US12437121B2Efficient processing of masked memory accessesSIFIVE INC·Filed 2021·Granted Oct 7, 2025·0 cites·20 claims
- 1852US12314191B2Memory protection for vector operationsSIFIVE INC·Filed 2021·Granted May 27, 2025·0 cites·23 claims
- 1951US2024020124A1Supporting Multiple Vector Lengths with Configurable Vector Register FileSIFIVE INC·Filed 2023·Application pending·0 cites
- 2051US2024020012A1Memory Request Combination IndicationSIFIVE INC·Filed 2023·Application pending·0 cites
- 2150US2023367599A1Vector Gather with a Narrow DatapathSIFIVE INC·Filed 2023·Application pending·0 cites
- 2249US2023019271A1Processor Power Management Using Instruction ThrottlingSIFIVE INC·Filed 2022·Application pending·0 cites
- 2346US11429392B2Secure predictors for speculative executionSIFIVE INC·Filed 2019·Granted Aug 30, 2022·0 cites·28 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →