Inventor · disambiguated record
Arnaud Castex
Also filed as: CASTEX ARNAUD
16 granted patents·8 pending applications·77 citations·filing 2009–2025
91Inventor score
Top patents by PatentIndex Score
24 records- 0193US8575002B2Direct bonding method with reduction in overlay misalignmentBROEKAART MARCEL·Filed 2011·Granted Nov 5, 2013·26 cites·18 claims
- 0288US8202785B2Surface treatment for molecular bondingCASTEX ARNAUD·Filed 2009·Granted Jun 19, 2012·19 cites·15 claims
- 0385US9004135B2Method and apparatus for bonding together two wafers by molecular adhesionCASTEX ARNAUD·Filed 2011·Granted Apr 14, 2015·9 cites·25 claims
- 0485US8163570B2Method of initiating molecular bondingCASTEX ARNAUD·Filed 2009·Granted Apr 24, 2012·11 cites·20 claims
- 0585US2024396520A1Heterostructure and method of fabricationSOITEC SILICON ON INSULATOR·Filed 2024·Application pending·0 cites
- 0683US11637542B2Heterostructure and method of fabricationSOITEC SILICON ON INSULATOR·Filed 2020·Granted Apr 25, 2023·1 cites·23 claims
- 0780US12101080B2Heterostructure and method of fabricationSOITEC SILICON ON INSULATOR·Filed 2023·Granted Sep 24, 2024·0 cites·19 claims
- 0880US10826459B2Heterostructure and method of fabricationSOITEC SILICON ON INSULATOR·Filed 2016·Granted Nov 3, 2020·2 cites·13 claims
- 0975US9733075B2System and method for assessing inhomogeneous deformations in multilayer platesBROEKAART MARCEL·Filed 2011·Granted Aug 15, 2017·3 cites·19 claims
- 1074US10886162B2Semiconductor-on-insulator substrate for RF applicationsSOITEC SILICON ON INSULATOR·Filed 2017·Granted Jan 5, 2021·1 cites·13 claims
- 1174US2023238274A1Semiconductor-on-insulator substrate for rf applicationsSOITEC SILICON ON INSULATOR·Filed 2023·Application pending·0 cites
- 1272US11626319B2Semiconductor-on-insulator substrate for rf applicationsSOITEC SILICON ON INSULATOR·Filed 2020·Granted Apr 11, 2023·0 cites·17 claims
- 1370US11595020B2Heterostructure and method of fabricationSOITEC SILICON ON INSULATOR·Filed 2020·Granted Feb 28, 2023·0 cites·27 claims
- 1467US8932938B2Method of fabricating a multilayer structure with circuit layer transferCASTEX ARNAUD·Filed 2010·Granted Jan 13, 2015·2 cites·16 claims
- 1564US2025140603A1Method for manufacturing a semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2025·Application pending·0 cites
- 1660US12230533B2Method for manufacturing a semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2020·Granted Feb 18, 2025·0 cites·10 claims
- 1759US8927320B2Method of bonding by molecular bondingLAGAHE BLANCHARD CHRYSTELLE·Filed 2010·Granted Jan 6, 2015·2 cites·20 claims
- 1857US9905531B2Method for producing composite structure with metal/metal bondingSOITEC SILICON ON INSULATOR·Filed 2013·Granted Feb 27, 2018·1 cites·9 claims
- 1951US2010155882A1Method for bonding two substratesCASTEX ARNAUD·Filed 2009·Application pending·0 cites
- 2047US2011287604A1Methods of forming semiconductor structures comprising direct bonding of substratesCASTEX ARNAUD·Filed 2011·Application pending·0 cites
- 2147US2012322229A1Method for bonding two substratesCASTEX ARNAUD·Filed 2012·Application pending·0 cites
- 2247US2013093033A9Three dimensional structures having improved alignments between layers of microcomponentsCASTEX ARNAUD·Filed 2011·Application pending·0 cites
- 2344US9548202B2Method for bonding by means of molecular adhesionSOITEC SILICON ON INSULATOR·Filed 2013·Granted Jan 17, 2017·0 cites·20 claims
- 2439US2024030883A1Process for manufacturing a piezoelectric structure for a radiofrequency device and which can be used to transfer a piezoelectric layer, and process for transferring such a piezoelectric layerSOITEC SILICON ON INSULATOR·Filed 2021·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →