Inventor · disambiguated record
Asher Berkovitz
Also filed as: BERKOVITZ ASHER
14 granted patents·1 pending application·19 citations·filing 2011–2015
87Inventor score
Top patents by PatentIndex Score
15 records- 0175US10746795B2Method and apparatus for at-speed scan shift frequency test optimizationSOFER SERGEY·Filed 2012·Granted Aug 18, 2020·3 cites·18 claims
- 0275US9709629B2Method and control device for launch-off-shift at-speed scan testingSOFER SERGEY·Filed 2013·Granted Jul 18, 2017·3 cites·15 claims
- 0372US9141753B2Method for placing operational cells in a semiconductor deviceROZEN ANTON·Filed 2011·Granted Sep 22, 2015·3 cites·19 claims
- 0465US9171117B2Method for ranking paths for power optimization of an integrated circuit design and corresponding computer program productBERKOVITZ ASHER·Filed 2011·Granted Oct 27, 2015·3 cites·20 claims
- 0564US9836567B2Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuitBERKOVITZ ASHER·Filed 2012·Granted Dec 5, 2017·3 cites·19 claims
- 0660US9903916B2Scan test system with a test interface having a clock control unit for stretching a power shift cycleSOFER SERGEY·Filed 2012·Granted Feb 27, 2018·1 cites·17 claims
- 0758US9542523B2Method and apparatus for selecting data path elements for cloningPRIEL MICHAEL·Filed 2012·Granted Jan 10, 2017·1 cites·13 claims
- 0855US9038006B2Method and apparatus for generating gate-level activity data for use in clock gating efficiency analysisFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted May 19, 2015·1 cites·20 claims
- 0948US10102329B2Method and apparatus for validating a test patternFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted Oct 16, 2018·0 cites·19 claims
- 1047US9607117B2Method and apparatus for calculating delay timing values for an integrated circuit designBERKOVITZ ASHER·Filed 2013·Granted Mar 28, 2017·0 cites·13 claims
- 1146US9977849B2Method and apparatus for calculating delay timing values for an integrated circuit designSOFER SERGEY·Filed 2013·Granted May 22, 2018·0 cites·16 claims
- 1246US9235673B2Apparatus for and a method of making a hierarchical integrated circuit design of an integrated circuit design, a computer program product and a non-transitory tangible computer readable storage mediumGRINSHPON AMIR·Filed 2014·Granted Jan 12, 2016·1 cites·20 claims
- 1344US9652572B2Method and apparatus for performing logic synthesisFREESCALE SEMICONDUCTOR INC·Filed 2013·Granted May 16, 2017·0 cites·13 claims
- 1435US9792399B2Integrated circuit hierarchical design tool apparatus and method of hierarchically designing an integrated circuitBERKOVITZ ASHER·Filed 2013·Granted Oct 17, 2017·0 cites·15 claims
- 1526US2016377676A1Integrated circuit including overlapping scan domainsFREESCALE SEMICONDUCTOR INC·Filed 2015·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Asher Berkovitz files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →