Inventor · disambiguated record
Ashok S. Prabhu
Also filed as: PRABHU ASHOK · PRABHU ASHOK S · PRABHU ASHOK SURENDRA
55 granted patents·12 pending applications·1,391 citations·filing 1999–2025
99Inventor score
Files withINVENSAS CORP22NAT SEMICONDUCTOR CORP22TEXAS INSTRUMENTS INC15ADEIA SEMICONDUCTOR TECH LLC2INVENSAS LLC2
Top patents by PatentIndex Score
67 records- 0198US10115678B2Wire bond wires for interference shieldingINVENSAS CORP·Filed 2017·Granted Oct 30, 2018·26 cites·20 claims
- 0298US9812402B2Wire bond wires for interference shieldingINVENSAS CORP·Filed 2016·Granted Nov 7, 2017·30 cites·20 claims
- 0398US6384397B1Low cost die sized module for imaging application having a lens housing assemblyNAT SEMICONDUCTOR CORP·Filed 2000·Granted May 7, 2002·215 cites·17 claims
- 0497US11810867B2Wire bond wires for interference shieldingINVENSAS LLC·Filed 2022·Granted Nov 7, 2023·2 cites·28 claims
- 0597US10181457B2Microelectronic package for wafer-level chip scale packaging with fan-outINVENSAS CORP·Filed 2016·Granted Jan 15, 2019·19 cites·6 claims
- 0697US9490222B1Wire bond wires for interference shieldingINVENSAS CORP·Filed 2015·Granted Nov 8, 2016·20 cites·20 claims
- 0796US10559537B2Wire bond wires for interference shieldingINVENSAS CORP·Filed 2018·Granted Feb 11, 2020·10 cites·18 claims
- 0896US9984992B2Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfacesINVENSAS CORP·Filed 2016·Granted May 29, 2018·27 cites·22 claims
- 0996US9490195B1Wafer-level flipped die stacks with leadframes or metal foil interconnectsINVENSAS CORP·Filed 2015·Granted Nov 8, 2016·27 cites·28 claims
- 1096US8679896B2DC/DC converter power module package incorporating a stacked controller and construction methodologyNAT SEMICONDUCTOR CORP·Filed 2013·Granted Mar 25, 2014·23 cites·7 claims
- 1196US6607941B2Process and structure improvements to shellcase style packaging technologyNAT SEMICONDUCTOR CORP·Filed 2002·Granted Aug 19, 2003·141 cites·17 claims
- 1295US10490528B2Embedded wire bond wiresINVENSAS CORP·Filed 2016·Granted Nov 26, 2019·17 cites·10 claims
- 1395US6791072B1Method and apparatus for forming curved image sensor moduleNAT SEMICONDUCTOR CORP·Filed 2002·Granted Sep 14, 2004·104 cites·2 claims
- 1494US9972609B2Package-on-package devices with WLP components with dual RDLs for surface mount dies and methods thereforINVENSAS CORP·Filed 2016·Granted May 15, 2018·8 cites·9 claims
- 1594US6238949B1Method and apparatus for forming a plastic chip on chip package moduleNAT SEMICONDUCTOR CORP·Filed 1999·Granted May 29, 2001·156 cites·15 claims
- 1693US10354976B2Dies-on-package devices and methods thereforINVENSAS CORP·Filed 2016·Granted Jul 16, 2019·6 cites·16 claims
- 1793US10043779B2Packaged microelectronic device for a package-on-package deviceINVENSAS CORP·Filed 2016·Granted Aug 7, 2018·8 cites·17 claims
- 1892US9911718B2‘RDL-First’ packaged microelectronic device for a package-on-package deviceINVENSAS CORP·Filed 2016·Granted Mar 6, 2018·7 cites·18 claims
- 1992US8674418B2Method and apparatus for achieving galvanic isolation in package having integral isolation mediumPODDAR ANINDYA·Filed 2011·Granted Mar 18, 2014·14 cites·15 claims
- 2092US7102209B1Substrate for use in semiconductor manufacturing and method of making sameNAT SEMICONDUCTOR CORP·Filed 2003·Granted Sep 5, 2006·91 cites·28 claims
- 2192US6781244B2Electrical die contact structure and fabrication methodNAT SEMICONDUCTOR CORP·Filed 2002·Granted Aug 24, 2004·55 cites·9 claims
- 2291US12021019B2Semiconductor device package with thermal padTEXAS INSTRUMENTS INC·Filed 2021·Granted Jun 25, 2024·2 cites·20 claims
- 2391US10325877B2Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfacesINVENSAS CORP·Filed 2018·Granted Jun 18, 2019·7 cites·20 claims
- 2491US9991235B2Package on-package devices with upper RDL of WLPS and methods thereforINVENSAS CORP·Filed 2016·Granted Jun 5, 2018·5 cites·9 claims
- 2591US9991233B2Package-on-package devices with same level WLP components and methods thereforINVENSAS CORP·Filed 2016·Granted Jun 5, 2018·5 cites·19 claims
- 2690US11462483B2Wire bond wires for interference shieldingINVENSAS LLC·Filed 2019·Granted Oct 4, 2022·3 cites·24 claims
- 2790US7067354B2Electrical die contact structure and fabrication methodNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 27, 2006·40 cites·11 claims
- 2888US7795126B2Electrical die contact structure and fabrication methodNAT SEMICONDUCTOR CORP·Filed 2008·Granted Sep 14, 2010·12 cites·24 claims
- 2988US7615407B1Methods and systems for packaging integrated circuits with integrated passive componentsNAT SEMICONDUCTOR CORP·Filed 2008·Granted Nov 10, 2009·17 cites·20 claims
- 3087US9985007B2Package on-package devices with multiple levels and methods thereforINVENSAS CORP·Filed 2016·Granted May 29, 2018·3 cites·29 claims
- 3187US9972573B2Wafer-level packaged components and methods thereforINVENSAS CORP·Filed 2016·Granted May 15, 2018·3 cites·20 claims
- 3286US12255153B2Wire bond wires for interference shieldingADEIA SEMICONDUCTOR TECH LLC·Filed 2023·Granted Mar 18, 2025·0 cites·25 claims
- 3384US6352881B1Method and apparatus for forming an underfill adhesive layerNAT SEMICONDUCTOR CORP·Filed 1999·Granted Mar 5, 2002·70 cites·8 claims
- 3482US7087986B1Solder pad configuration for use in a micro-array integrated circuit packageNAT SEMICONDUCTOR CORP·Filed 2004·Granted Aug 8, 2006·33 cites·19 claims
- 3582US6933597B1Spacer with passive components for use in multi-chip modulesNAT SEMICONDUCTOR CORP·Filed 2002·Granted Aug 23, 2005·33 cites·9 claims
- 3682US2025253264A1Wire bond wires for interference shieldingADEIA SEMICONDUCTOR TECH LLC·Filed 2025·Application pending·0 cites
- 3779US7491625B2Gang flipping for IC packagingNAT SEMICONDUCTOR CORP·Filed 2007·Granted Feb 17, 2009·9 cites·13 claims
- 3878US9825002B2Flipped die stackINVENSAS CORP·Filed 2016·Granted Nov 21, 2017·3 cites·12 claims
- 3976US11021786B2Copper passivationTEXAS INSTRUMENTS INC·Filed 2018·Granted Jun 1, 2021·2 cites·38 claims
- 4076US10763231B2Bump bond structure for enhanced electromigration performanceTEXAS INSTRUMENTS INC·Filed 2018·Granted Sep 1, 2020·2 cites·12 claims
- 4176US7186588B1Method of fabricating a micro-array integrated circuit packageNAT SEMICONDUCTOR CORP·Filed 2004·Granted Mar 6, 2007·27 cites·7 claims
- 4276US6364089B1Multi-station rotary die handling deviceNAT SEMICONDUCTOR CORP·Filed 1999·Granted Apr 2, 2002·46 cites·28 claims
- 4372US7064419B1Die attach region for use in a micro-array integrated circuit packageNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 20, 2006·23 cites·19 claims
- 4471US2024347441A1Semiconductor device package with thermal padTEXAS INSTRUMENTS INC·Filed 2024·Application pending·0 cites
- 4570US10763230B2Integrated circuit backside metallizationTEXAS INSTRUMENTS INC·Filed 2018·Granted Sep 1, 2020·1 cites·8 claims
- 4670US7259460B1Wire bonding on thinned portions of a lead-frame configured for use in a micro-array integrated circuit packageNAT SEMICONDUCTOR CORP·Filed 2004·Granted Aug 21, 2007·21 cites·7 claims
- 4765US11367699B2Integrated circuit backside metallizationTEXAS INSTRUMENTS INC·Filed 2020·Granted Jun 21, 2022·0 cites·19 claims
- 4864US10650957B1Additive deposition low temperature curable magnetic interconnecting layer for power components integrationTEXAS INSTRUMENTS INC·Filed 2018·Granted May 12, 2020·0 cites·23 claims
- 4964US9871019B2Flipped die stack assemblies with leadframe interconnectsINVENSAS CORP·Filed 2016·Granted Jan 16, 2018·1 cites·13 claims
- 5064US7205095B1Apparatus and method for packaging image sensing semiconductor chipsNAT SEMICONDUCTOR CORP·Filed 2003·Granted Apr 17, 2007·10 cites·10 claims
Showing the top 50 of 67 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →