Inventor · disambiguated record
Atul Ajmera
Also filed as: AJMERA ATUL · AJMERA ATUL C · AJMERA ATUL CHAMPAKLAL
23 granted patents·4 pending applications·701 citations·filing 1995–2013
97Inventor score
Top patents by PatentIndex Score
27 records- 0198US7759206B2Methods of forming semiconductor devices using embedded L-shape spacersIBM·Filed 2005·Granted Jul 20, 2010·118 cites·9 claims
- 0294US6503833B1Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed therebyIBM·Filed 2000·Granted Jan 7, 2003·83 cites·35 claims
- 0392US6991979B2Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETsIBM·Filed 2003·Granted Jan 31, 2006·52 cites·9 claims
- 0486US6440807B1Surface engineering to prevent EPI growth on gate poly during selective EPI processingIBM·Filed 2001·Granted Aug 27, 2002·31 cites·20 claims
- 0585US6566210B2Method of improving gate activation by employing atomic oxygen enhanced oxidationIBM·Filed 2001·Granted May 20, 2003·35 cites·20 claims
- 0683US6566198B2CMOS structure with non-epitaxial raised source/drain and self-aligned gate and method of manufactureIBM·Filed 2001·Granted May 20, 2003·32 cites·17 claims
- 0783US6506649B2Method for forming notch gate having self-aligned raised source/drain structureIBM·Filed 2001·Granted Jan 14, 2003·33 cites·13 claims
- 0880US7091128B2Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETsIBM·Filed 2005·Granted Aug 15, 2006·6 cites·10 claims
- 0977US6521947B1Method of integrating substrate contact on SOI wafers with STI processIBM·Filed 1999·Granted Feb 18, 2003·50 cites·16 claims
- 1077US6013583ALow temperature BPSG deposition processIBM·Filed 1996·Granted Jan 11, 2000·50 cites·16 claims
- 1176US6437377B1Low dielectric constant sidewall spacer using notch gate processIBM·Filed 2001·Granted Aug 20, 2002·21 cites·19 claims
- 1275US6057220ATitanium polycide stabilization with a porous barrierIBM·Filed 1997·Granted May 2, 2000·36 cites·11 claims
- 1375US5747866AApplication of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structuresSIEMENS AG·Filed 1997·Granted May 5, 1998·41 cites·13 claims
- 1475US5643823AApplication of thin crystalline Si3 N4 liners in shallow trench isolation (STI) structuresSIEMENS AG·Filed 1995·Granted Jul 1, 1997·45 cites·5 claims
- 1574US6605521B2Method of forming an oxide film on a gate side wall of a gate structureTOSHIBA KK·Filed 2002·Granted Aug 12, 2003·21 cites·19 claims
- 1670US7387924B2Polycrystalline SiGe junctions for advanced devicesIBM·Filed 2006·Granted Jun 17, 2008·2 cites·1 claims
- 1770US6900092B2Surface engineering to prevent epi growth on gate poly during selective epi processingIBM·Filed 2002·Granted May 31, 2005·11 cites·17 claims
- 1868US6642156B2Method for forming heavy nitrogen-doped ultra thin oxynitride gate dielectricsIBM·Filed 2001·Granted Nov 4, 2003·11 cites·11 claims
- 1958US7741165B2Polycrystalline SiGe Junctions for advanced devicesIBM·Filed 2008·Granted Jun 22, 2010·0 cites·12 claims
- 2056US6602759B2Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysiliconIBM·Filed 2000·Granted Aug 5, 2003·7 cites·26 claims
- 2156US6255145B1Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting productIBM·Filed 1999·Granted Jul 3, 2001·16 cites·20 claims
- 2247US2013256766A1Spacer and process to enhance the strain in the channel with stress linerIBM·Filed 2013·Application pending·0 cites
- 2341US8461009B2Spacer and process to enhance the strain in the channel with stress linerAJMERA ATUL C·Filed 2006·Granted Jun 11, 2013·0 cites·16 claims
- 2440US7135391B2Polycrystalline SiGe junctions for advanced devicesIBM·Filed 2004·Granted Nov 14, 2006·0 cites·14 claims
- 2540US2001041395A1Planar substrate with patterned silicon-on- insulator region and self-aligned trenchFiled 2001·Application pending·0 cites
- 2639US2007254420A1Source/drain implantation and channel strain transfer using different sized spacers and related semiconductor deviceIBM·Filed 2006·Application pending·0 cites
- 2737US2003068883A1Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed therebyIBM·Filed 2002·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Atul Ajmera files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →