Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed thereby

Abstract

A method of forming a semiconductor substrate (and resultant structure), includes providing a semiconductor substrate to be silicided including a source and drain formed therein on respective sides of a gate, depositing a metal film over the gate, source and drain regions, reacting the metal film with Si at a first predetermined temperature, to form a metal-silicon alloy, etching the unreacted metal, depositing a silicon film over the source drain and gate regions, annealing the substrate at a second predetermined temperature, to form a metal-Si 2 alloy, and selectively etching the unreacted Si.

Having thus described our invention, what we claim as new and desire to secure by Letters Patent is as follows:  
     
         1 . A method of forming a semiconductor substrate, comprising: 
 providing a semiconductor substrate to be silicided including a substrate having a source region and a drain region formed therein on respective sides of a gate;    forming a metal film over the gate, source and drain regions;    reacting said metal film with Si at a first predetermined temperature, to form a metal-silicon alloy;    forming a silicon film onto the metal-silicon alloy;    annealing the substrate at a second predetermined temperature, to form a metal-Si 2  alloy; and    selectively etching said unreacted Si.    
     
     
         2 . The method of  claim 1 , wherein said metal includes at least one of Co, Ti, Pd, and Pt.  
     
     
         3 . The method of  claim 1 , wherein said thin film of metal has a thickness of approximately 0.3 nm to approximately 50 nm.  
     
     
         4 . The method of  claim 1 , wherein said metal film is cobalt.  
     
     
         5 . The method of  claim 4 , wherein said predetermined temperature is between about 481 C to about 625 C.  
     
     
         6 . The method of  claim 5 , further comprising: 
 selectively etching any unreacted metal.    
     
     
         7 . The method of  claim 1 , wherein said silicon film comprises one of an amorphous Si (a-Si) and a poly-Si film.  
     
     
         8 . The method of  claim 1 , wherein said silicon film has a thickness of between about 15 nm to about 75 nm.  
     
     
         9 . The method of  claim 1 , wherein said process is devoid of a selective epitaxy of the source and drain regions.  
     
     
         10 . The method of  claim 1 , wherein said substrate is Si 0 7 Ge 0 3 .  
     
     
         11 . The method of  claim 10 , wherein said second predetermined temperature is higher than approximately 825 C.  
     
     
         12 . The method of  claim 1 , wherein said substrate is Si 1-x Ge x , where x is between 0.05 to 0.4.  
     
     
         13 . The method of  claim 1 , wherein said metal-Si 2  formation occurs only in the deposited silicon film.  
     
     
         14 . The method of  claim 1 , wherein the semiconductor substrate further comprises a relaxed SiGe buffer layer, a strained Si film, a gate dielectric, a patterned gate, and first and second sidewall spacers, formed in this order on said substrate.  
     
     
         15 . The method of  claim 1 , wherein said second predetermined temperature is higher than said first predetermined temperature.  
     
     
         16 . The method of  claim 1 , wherein said silicon film comprises a strained silicon, and wherein said first annealing consumes substantially all of the strained silicon.  
     
     
         17 . The method of  claim 1 , wherein said silicon film comprises a strained silicon, and wherein said first annealing consumes a portion of the strained silicon.  
     
     
         18 . The method of  claim 16 , wherein said substrate includes a Si—Ge buffer layer, and wherein said first annealing further consumes a portion of the silicon in the Si—Ge buffer layer.  
     
     
         19 . The method of  claim 1 , wherein said method is self-aligned and is devoid of using any of a patterning and a mask.  
     
     
         20 . The method of  claim 1 , wherein said metal film is co-sputtered with silicon, a percentage of said silicon to said metal film being less than 28%.  
     
     
         21 . The method of  claim 1 , wherein said substrate is a Si 1-x Ge x  composition, where 0.05<x<0.5.  
     
     
         22 . The method of  claim 13 , wherein said silicon film comprises a strained silicon film, and wherein, if not all of the strained silicon film is reacted with the metal film to form metal-Si during the first anneal, then the remaining silicon in the strained silicon film reacts to form the metal-Si 2  phase.  
     
     
         23 . The method of  claim 1 , wherein the metal film comprises pure metal.  
     
     
         24 . The method of  claim 1 , wherein the metal film comprises a metal-silicon mixture.  
     
     
         25 . The method of  claim 24 , wherein the first anneal forms a metal-rich phase, and the unreacted metal-silicon mixture is etched.  
     
     
         26 . The method of  claim 25 , wherein a Si cap is deposited over the metal-rich phase and annealed to form the disilicide.  
     
     
         27 . The method of  claim 1 , further comprising: 
 after said reacting, etching any unreacted portion of the metal.    
     
     
         28 . A method of forming a silicide, including: 
 providing a substrate to be silicided including forming a metal-silicon mixture over predetermined regions of said substrate;    reacting said metal-silicon mixture with Si at a first predetermined temperature, to form a metal-rich phase;    etching any unreacted portion of the metal-silicon mixture;    depositing a silicon cap over the metal-rich phase;    annealing the substrate at a second predetermined temperature, to form a metal-Si, alloy; and    selectively etching said unreacted Si.    
     
     
         29 . A method of forming a semiconductor substrate, comprising: 
 providing a semiconductor substrate to be silicided including a substrate having a source region and a drain region formed therein on respective sides of a gate;    forming a metal-silicon mixture over the gate, source and drain regions;    reacting said metal-silicon mixture with Si at a first predetermined temperature, to form a metal-rich phase;    etching any unreacted portion of the metal-silicon mixture;    depositing a silicon cap over the metal-rich phase;    annealing the substrate at a second predetermined temperature, to form a metal-Si 2  alloy; and    selectively etchinu said unreacted Si.    
     
     
         30 . The method of  claim 29 , wherein said metal-rich phase is Co 2 Si.  
     
     
         31 . A method of siliciding a substrate, comprising: 
 providing a substrate to be silicided forming a metal film over the substrate;    reacting said metal film with Si at a first predetermined temperature, to form a metal-silicon alloy;    etching the unreacted metal;    forming a silicon film over said metal-silicon alloy;    annealing the substrate at a second predetermined temperature, to form a metal-Si 2  alloy; and    selectively etching said unreacted Si.    
     
     
         32 . A semiconductor substrate, comprising: 
 a substrate;    a relaxed Si—Ge buffer layer formed on said substrate;    a strained silicon layer formed on said Si—Ge buffer layer and having a source and drain formed therein on respective sides of a gate, said gate being formed over said strained silicon; and    a metal film deposited over the gate, source and drain regions, said metal film having been reacted with Si at a first predetermined temperature, to form a metal-silicon alloy,    wherein said source drain and gate are formed of a metal disilicide, and    wherein said source and drain are raised over said strained silicon layer.