Inventor · disambiguated record
Ronnen Andrew Roy
Also filed as: ROY RONNEN A · ROY RONNEN ANDREW
30 granted patents·4 pending applications·946 citations·filing 1984–2005
98Inventor score
Top patents by PatentIndex Score
34 records- 0195US5796166ATasin oxygen diffusion barrier in multilayer structuresIBM·Filed 1996·Granted Aug 18, 1998·122 cites·7 claims
- 0294US6503833B1Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed therebyIBM·Filed 2000·Granted Jan 7, 2003·83 cites·35 claims
- 0392US6555880B2Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed therebyIBM·Filed 2001·Granted Apr 29, 2003·54 cites·9 claims
- 0492US5576579ATasin oxygen diffusion barrier in multilayer structuresIBM·Filed 1995·Granted Nov 19, 1996·83 cites·4 claims
- 0590US5776823ATasin oxygen diffusion barrier in multilayer structuresIBM·Filed 1996·Granted Jul 7, 1998·67 cites·6 claims
- 0689US6440808B1Damascene-gate process for the fabrication of MOSFET devices with minimum poly-gate depletion, silicided source and drain junctions, and low sheet resistance gate-polyIBM·Filed 2000·Granted Aug 27, 2002·48 cites·20 claims
- 0788US7259049B2Self-aligned isolation double-gate FETIBM·Filed 2005·Granted Aug 21, 2007·11 cites·12 claims
- 0888US6440851B1Method and structure for controlling the interface roughness of cobalt disilicideIBM·Filed 1999·Granted Aug 27, 2002·57 cites·24 claims
- 0987US5828131ALow temperature formation of low resistivity titanium silicideIBM·Filed 1996·Granted Oct 27, 1998·60 cites·6 claims
- 1085US6946696B2Self-aligned isolation double-gate FETIBM·Filed 2002·Granted Sep 20, 2005·29 cites·18 claims
- 1184US6410430B1Enhanced ultra-shallow junctions in CMOS using high temperature silicide processIBM·Filed 2000·Granted Jun 25, 2002·31 cites·28 claims
- 1282US6614079B2All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOSIBM·Filed 2001·Granted Sep 2, 2003·25 cites·11 claims
- 1381US6987050B2Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk MOSFETS and for shallow junctionsIBM·Filed 2001·Granted Jan 17, 2006·21 cites·28 claims
- 1481US6413859B1Method and structure for retarding high temperature agglomeration of silicides using alloysIBM·Filed 2000·Granted Jul 2, 2002·26 cites·3 claims
- 1580US7074684B2Elevated source drain disposable spacer CMOSIBM·Filed 2004·Granted Jul 11, 2006·20 cites·1 claims
- 1680US6331486B1Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloyIBM·Filed 2000·Granted Dec 18, 2001·21 cites·22 claims
- 1778US6716708B2Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed therebyIBM·Filed 2002·Granted Apr 6, 2004·20 cites·31 claims
- 1874US6972250B2Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned CoSi2 on raised source drain Si/SiGe deviceIBM·Filed 2003·Granted Dec 6, 2005·16 cites·18 claims
- 1974US6727135B2All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOSIBM·Filed 2003·Granted Apr 27, 2004·16 cites·22 claims
- 2074US6690072B2Method and structure for ultra-low contact resistance CMOS formed by vertically self-aligned COSI2 on raised source drain Si/SiGe deviceIBM·Filed 2002·Granted Feb 10, 2004·16 cites·3 claims
- 2173US6753606B2Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloyIBM·Filed 2001·Granted Jun 22, 2004·13 cites·11 claims
- 2273US6316123B1Microwave annealingIBM·Filed 2000·Granted Nov 13, 2001·15 cites·3 claims
- 2368US4675302ALow expansion ceramic materialPERKIN ELMER CORP·Filed 1984·Granted Jun 23, 1987·23 cites·30 claims
- 2467US6051283AMicrowave annealingIBM·Filed 1998·Granted Apr 18, 2000·22 cites·23 claims
- 2565US6777298B2Elevated source drain disposable spacer CMOSIBM·Filed 2002·Granted Aug 17, 2004·8 cites·16 claims
- 2656US7081676B2Structure for controlling the interface roughness of cobalt disilicideIBM·Filed 2003·Granted Jul 25, 2006·5 cites·8 claims
- 2755US5206213AMethod of preparing oriented, polycrystalline superconducting ceramic oxidesIBM·Filed 1990·Granted Apr 27, 1993·20 cites·25 claims
- 2851US7102234B2Method and structure for reduction of contact resistance of metal silicides using a metal-germanium alloyIBM·Filed 2004·Granted Sep 5, 2006·3 cites·7 claims
- 2949US6187679B1Low temperature formation of low resistivity titanium silicideIBM·Filed 1997·Granted Feb 13, 2001·9 cites·14 claims
- 3047US6809030B2Method and structure for controlling the interface roughness of cobalt disilicideIBM·Filed 2002·Granted Oct 26, 2004·2 cites·9 claims
- 3141US2006043484A1Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctionsIBM·Filed 2004·Application pending·0 cites
- 3237US2002031909A1Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfetsFiled 2000·Application pending·0 cites
- 3337US2002151158A1Method and structure for retarding high temperature agglomeration of silicides using alloysIBM·Filed 2002·Application pending·0 cites
- 3437US2003068883A1Self-aligned silicide (salicide) process for strained silicon MOSFET on SiGe and structure formed therebyIBM·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →