Self-aligned silicone process for low resistivity contacts to thin film silicon-on-insulator mosfets

Abstract

A silicide processing method for a thin film SOI device including depositing a metal or an alloy on a gate and a source/drain structure formed in a silicon-on-insulator film, reacting the metal or alloy at a first temperature with the silicon-on-insulator film to form a first alloy, etching the unreacted layer of the metal (or alloy) selectively, depositing a Si film on the first alloy, reacting the Si film at a second temperature to form a second alloy, and etching the unreacted layer of the Si film selectively.

What is claimed is:  
     
         1 . A method for fabricating a silicide for a semiconductor device, said method comprising: 
 depositing a buried oxide layer on a substrate;    applying a silicon layer to said buried oxide layer;    forming a source and drain in said silicon layer;    forming a gate on said layer of silicon; and    depositing a metal or an alloy on said gate and said source and drain, to form said silicide for said semiconductor device.    
     
     
         2 . The method, as claimed in  claim 1 , further comprising: 
 reacting said metal or said alloy with said silicon to form a first alloy at said gate and said source/drain structure.    
     
     
         3 . The method, as claimed in  claim 1 , wherein said semiconductor device comprises a metal oxide semiconductor field-effect transistor (MOSFET) device.  
     
     
         4 . The method, as claimed in  claim 1 , wherein said metal is selected from one of a group consisting of cobalt, titanium, nickel, platinum, Pt x  Si 1-x  alloy, palladium, Pd x  Si 1-x  alloy, and Co x  Si 1-x  alloy.  
     
     
         5 . The method, as claimed in  claim 2 , wherein said reacting is performed at a first temperature.  
     
     
         6 . The method, as claimed in  claim 2 , wherein said reacting is performed within a range of a first predetermined lower temperature to a second predetermined higher temperature.  
     
     
         7 . The method, as claimed in  claim 6 , wherein said reacting is performed at a third temperature, said third temperature being intermediate said first and second temperatures.  
     
     
         8 . The method, as claimed in  claim 2 , wherein said first alloy is an alloy selected from the group consisting of Co 2  Si and Co Si.  
     
     
         9 . The method, as claimed in  claim 2 , wherein said first alloy is formed under an unreacted layer of said metal or said alloy.  
     
     
         10 . The method, as claimed in  claim 9 , further comprising: 
 etching said unreacted layer of said metal or said alloy selectively;    depositing a Si film on said first alloy; and    reacting said Si film to form a second alloy.    
     
     
         11 . The method, as claimed in  claim 10 , wherein said film is a film selected from the group consisting of a single crystal Si film and a polysilicon film.  
     
     
         12 . The method, as claimed in  claim 10 , wherein said reacting said Si film is performed at a second temperature.  
     
     
         13 . The method, as claimed in  claim 10 , wherein said second alloy is formed under an unreacted layer of said Si film.  
     
     
         14 . The method, as claimed in  claim 13 , wherein said second alloy is CoSi 2 .  
     
     
         15 . The method, as claimed in  claim 13 , further comprising: 
 etching said unreacted layer of said Si film selectively.    
     
     
         16 . A silicide processing method for a thin film silicon-on-insulator (SOI) device, said method comprising: 
 depositing a metal or an alloy on a gate and a source and drain formed in a silicon-on-insulator (SOI) film;    reacting said metal or said alloy at a first temperature with said SOI film to form a first alloy;    selectively etching said unreacted layer of said metal or said alloy;    depositing a Si film on said first alloy; and    reacting said Si film at a second temperature to form a second alloy.    
     
     
         17 . The method, as claimed in  claim 16 , wherein said reacting of said Si film at said second temperature reduces consumption of said silicon-on-insulator film by at least a factor of two.  
     
     
         18 . The method, as claimed in  claim 16 , further comprising selectively etching said unreacted layer of said metal or said alloy.  
     
     
         19 . The method, as claimed in  claim 16 , wherein said second temperature is greater than said first temperature.  
     
     
         20 . The method as claimed in  claim 16 , further comprising selectively etching said unreacted layer of said Si film.  
     
     
         21 . The method, as claimed in  claim 16 , wherein said metal is selected from one of a group consisting of cobalt, titanium, nickel, platinum, Pt x  Si 1-x  alloy, palladium, Pd x  Si 1-x  alloy, and Co x  Si 1-x  alloy.  
     
     
         22 . The method, as claimed in  claim 16 , wherein said reacting is performed within a range of a first predetermined lower temperature to a second predetermined higher temperature.  
     
     
         23 . The method, as claimed in  claim 16 , wherein said first alloy is an alloy selected from the group consisting of Co 2 Si and CoSi.  
     
     
         24 . The method, as claimed in  claim 16 , wherein said film is a film selected from the group consisting of a single crystal Si film and a polysilicon film.  
     
     
         25 . The method, as claimed in  claim 16 , wherein said second alloy is CoSi 2 .