Inventor · disambiguated record
Atsuhiro Suga
Also filed as: SUGA ATSUHIRO
17 granted patents·7 pending applications·390 citations·filing 1996–2013
94Inventor score
Top patents by PatentIndex Score
24 records- 0195US6681280B1Interrupt control apparatus and method separately holding respective operation information of a processor preceding a normal or a break interruptFUJITSU LTD·Filed 2000·Granted Jan 20, 2004·125 cites·13 claims
- 0285US6868472B1Method of Controlling and addressing a cache memory which acts as a random address memory to increase an access speed to a main memoryFUJITSU LTD·Filed 2000·Granted Mar 15, 2005·47 cites·6 claims
- 0374US5828860AData processing device equipped with cache memory and a storage unit for storing data between a main storage or CPU cache memoryFUJITSU LTD·Filed 1996·Granted Oct 27, 1998·97 cites·33 claims
- 0468US7581090B2Interrupt control apparatus and methodFUJITSU LTD·Filed 2003·Granted Aug 25, 2009·12 cites·21 claims
- 0564US8839210B2Program performance analysis apparatusKAMIGATA TERUHIKO·Filed 2009·Granted Sep 16, 2014·4 cites·15 claims
- 0663US8181171B2Method and apparatus for analyzing large scale program and generation of code from degenerated program dependence graphITO MAKIKO·Filed 2008·Granted May 15, 2012·3 cites·15 claims
- 0763US7028151B2Information processing device equipped with improved address queue register files for cache missFUJITSU LTD·Filed 2003·Granted Apr 11, 2006·10 cites·12 claims
- 0862US6775762B1Processor and processor systemFUJITSU LTD·Filed 2000·Granted Aug 10, 2004·9 cites·18 claims
- 0961US6889315B2Processor and method of controlling the sameFUJITSU LTD·Filed 2000·Granted May 3, 2005·8 cites·55 claims
- 1060US7401204B1Parallel Processor efficiently executing variable instruction wordFUJITSU LTD·Filed 2000·Granted Jul 15, 2008·8 cites·12 claims
- 1160US7376820B2Information processing unit, and exception processing method for specific application-purpose operation instructionFUJITSU LTD·Filed 2000·Granted May 20, 2008·10 cites·16 claims
- 1257US7134004B1Processing device for buffering sequential and target sequences and target address information for multiple branch instructionsFUJITSU LTD·Filed 2000·Granted Nov 7, 2006·7 cites·9 claims
- 1349US8549227B2Multiprocessor system and operating method of multiprocessor systemTAGO SHINICHIRO·Filed 2008·Granted Oct 1, 2013·0 cites·18 claims
- 1449US2008215859A1Computer with high-speed context switchingFUJITSU LTD·Filed 2008·Application pending·0 cites
- 1545US2006224870A1Information processing deviceTAGO SHIN-ICHIRO·Filed 2006·Application pending·0 cites
- 1643US6078993AData supplying apparatus for independently performing hit determination and data accessFUJITSU LTD·Filed 1996·Granted Jun 20, 2000·14 cites·17 claims
- 1743US2004093505A1Open generic tamper resistant CPU and application system thereofFUJITSU LTD·Filed 2003·Application pending·0 cites
- 1841US6374334B1Data processing apparatus with a cache controlling deviceFUJITSU LTD·Filed 1997·Granted Apr 16, 2002·15 cites·18 claims
- 1941US2014019738A1Multicore processor system and branch predicting methodFUJITSU LTD·Filed 2013·Application pending·0 cites
- 2040US6516407B1Information processorFUJITSU LTD·Filed 1999·Granted Feb 4, 2003·13 cites·17 claims
- 2140US2005289334A1Method for loading multiprocessor programFUJITSU LTD·Filed 2005·Application pending·0 cites
- 2240US2002078286A1Computer and control method of the computerFiled 2001·Application pending·0 cites
- 2338US2001049781A1Computer with high-speed context switchingFiled 2001·Application pending·0 cites
- 2436US6076145AData supplying apparatus for independently performing hit determination and data accessFUJITSU LTD·Filed 1998·Granted Jun 13, 2000·8 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →