Information processing device

Abstract

The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction; wherein, when the branching instruction detection portion has detected a branching instruction, either the branch target address information of the branching instruction is stored in one of the plurality of branch target address information buffers, or the branch target instruction sequence of the branching instruction is stored in one of the plurality of instruction buffers in addition to the storing in the branch target address information buffer.

1 - 11 . (canceled)  
   
   
       12 . An information processing device comprising: 
 an instruction fetch portion which fetches both a sequential side instruction sequence and a target side instruction sequence of a branching instruction;    a cache controller which fetches instructions from a cache memory or from a main memory in response to a fetch request from said instruction fetch portion;    a memory bus access portion which accesses said main memory;    an instruction buffer which buffers instructions which have been fetched; and    a branching prediction portion which, prior to an execution of a branching instruction, performs a branching prediction for the branching instruction which is stored in said instruction buffer;    wherein, while a branching direction of said branching instruction is not yet determined, if the cache controller has performed a cache miss, said cache controller performs or does not perform a memory bus access to said main memory depending on a branching direction predicted by the branching prediction portion.    
   
   
       13 . The information processing device as claimed in  claim 12  wherein, while the branching direction of said branching instruction is not yet determined, if the cache controller has performed the cache miss with respect to an instruction in the predicted branching direction of said branching instruction, said cache controller performs the memory bus access to the main memory for an instruction fetch, and if said cache controller has performed the cache miss with respect to an instruction which is not in the predicted branching direction, said cache controller does not perform the memory bus access and stops the instruction fetch.  
   
   
       14 . The information processing device as claimed in  claim 12  wherein, while the branching direction of said branching instruction is not yet determined and the predicted branching direction of said branching instruction is the sequential side, in the event of said cache controller performing the cache miss with respect to a target side instruction, said cache controller does not perform a memory bus access and stops the instruction fetch.  
   
   
       15 . The information processing device as claimed in  claim 12  wherein, while the branching direction of said branching instruction is not yet determined, said cache controller does not perform a memory bus access after the cache miss depending on the predicted branching direction of said branching instruction.  
   
   
       16 - 18 . (canceled)  
   
   
       19 . The information processing device as claimed in  claim 12  wherein the information processing device includes a pipeline processing.  
   
   
       20 . The information processing device as claimed in  claim 12  wherein the instruction fetch portion fetches both the sequential side instruction sequence and the target side instruction sequence of the branching instruction in spite of a branching prediction of the branching instruction.  
   
   
       21 . An information processing device comprising: 
 an instruction fetch portion adapted to fetch a sequential side instruction sequence and a target side instruction sequence of a branching instruction;    a cache controller adapted to fetch instructions from one of a cache memory and a main memory in response to a fetch request from the instruction fetch portion;    a memory bus access portion adapted to access the main memory;    an instruction buffer adapted to buffer instructions which have been fetched; and    a branching prediction portion adapted to perform, prior to an execution of a branching instruction, a branching prediction for the branching instruction which is stored in the instruction buffer;    wherein, while the branching direction of the branching instruction is not yet determined, if the cache controller performs a cache miss, the cache controller performs a memory bus access to the main memory according to an instruction of a branching direction predicted by the branching prediction portion.