Inventor · disambiguated record
Benjamin Crawford Chaffin
Also filed as: CHAFFIN BENJAMIN · CHAFFIN BENJAMIN C · CHAFFIN BENJAMIN CRAWFORD
18 granted patents·13 pending applications·26 citations·filing 2000–2024
90Inventor score
Technology areasG06F
Top patents by PatentIndex Score
31 records- 0185US9898351B2Method and apparatus for user-level thread synchronization with a monitor and MWAIT architectureINTEL CORP·Filed 2015·Granted Feb 20, 2018·6 cites·18 claims
- 0277US9703566B2Sharing TLB mappings between contextsCOMBS JONATHAN D·Filed 2011·Granted Jul 11, 2017·5 cites·20 claims
- 0377US8522044B2Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2010·Granted Aug 27, 2013·3 cites·7 claims
- 0474US10175986B2Stateless capture of data linear addresses during precise event based samplingINTEL CORP·Filed 2017·Granted Jan 8, 2019·2 cites·20 claims
- 0564US12020031B2Methods, apparatus, and instructions for user-level thread suspensionINTEL CORP·Filed 2021·Granted Jun 25, 2024·0 cites·18 claims
- 0664US7793111B1Mechanism to handle events in a machine with isolated executionINTEL CORP·Filed 2000·Granted Sep 7, 2010·7 cites·18 claims
- 0762US9715432B2Memory fault suppression via re-execution and hardware FSMINTEL CORP·Filed 2014·Granted Jul 25, 2017·1 cites·16 claims
- 0860US9652237B2Stateless capture of data linear addresses during precise event based samplingGRAMUNT ROGER·Filed 2014·Granted May 16, 2017·2 cites·20 claims
- 0959US11586537B2Method, apparatus, and system for run-time checking of memory tags in a processor-based systemAMPERE COMPUTING LLC·Filed 2021·Granted Feb 21, 2023·0 cites·33 claims
- 1058US12346264B2Performing instruction fetch pipeline synchronization (IFPS) in processor-based devicesAMPERE COMPUTING LLC·Filed 2023·Granted Jul 1, 2025·0 cites·20 claims
- 1157US12379931B2Mechanism for instruction fusionAMPERE COMPUTING LLC·Filed 2023·Granted Aug 5, 2025·0 cites·21 claims
- 1257US12333001B2Mitigation of return stack buffer side channel attacks in a processorAMPERE COMPUTING LLC·Filed 2021·Granted Jun 17, 2025·0 cites·30 claims
- 1356US2025291735A1Multi-core processor-based system implementing directed page table entry invalidationAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 1455US12493552B1Performing snoop filter replacement based on history-augmented victimization priority values of snoop filter entries in processor-based devicesAMPERE COMPUTING LLC·Filed 2024·Granted Dec 9, 2025·0 cites·30 claims
- 1554US2025130945A1System and method for handling cache updatesAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 1653US2025103506A1Processors with toggleable memory tagging extensions and related methodsAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 1753US2025130852A1Apparatus and method of workload throttling in a mesh networkAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 1853US2025110902A1Processors employing default tags for writes to memory from devices not compliant with a memory tagging extension and related methodsAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 1952US11023233B2Methods, apparatus, and instructions for user level thread suspensionINTEL CORP·Filed 2016·Granted Jun 1, 2021·0 cites·15 claims
- 2052US2025130799A1Techniques for performing non-vector micro-operations on vector hardwareAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 2152US2025130804A1Techniques for optimizing store of common values to memory structuresAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 2252US2024232090A1Multi-trained scalable prefetcher, and related methodsAMPERE COMPUTING LLC·Filed 2024·Application pending·0 cites
- 2351US8671275B2Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2010·Granted Mar 11, 2014·0 cites·9 claims
- 2451US8458464B2Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2010·Granted Jun 4, 2013·0 cites·4 claims
- 2550US2025130807A1Processor macro-operation fusionAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 2649US9804842B2Method and apparatus for efficiently managing architectural register state of a processorINTEL CORP·Filed 2014·Granted Oct 31, 2017·0 cites·20 claims
- 2748US2025130798A1Providing additional operations for a functional unit of a processor coreAMPERE COMPUTING LLC·Filed 2023·Application pending·0 cites
- 2848US2005283660A1Mechanism to handle events in a machine with isolated executionMCKEEN FRANCIS X·Filed 2005·Application pending·0 cites
- 2945US9886396B2Scalable event handling in multi-threaded processor coresINTEL CORP·Filed 2014·Granted Feb 6, 2018·0 cites·15 claims
- 3043US2007260907A1Technique to modify a timerDIXON MARTIN G·Filed 2006·Application pending·0 cites
- 3140US2002129229A1Microinstruction sequencer stackFiled 2000·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →