Inventor · disambiguated record
Benoit De Lescure
Also filed as: DE LESCURE BENOIT
34 granted patents·9 pending applications·165 citations·filing 2010–2025
96Inventor score
Top patents by PatentIndex Score
43 records- 0197US11449655B2Synthesis of a network-on-chip (NoC) using performance constraints and objectivesARTERIS INC·Filed 2020·Granted Sep 20, 2022·18 cites·17 claims
- 0296US11121933B2Physically aware topology synthesis of a networkARTERIS INC·Filed 2019·Granted Sep 14, 2021·27 cites·14 claims
- 0396US10990724B1System and method for incremental topology synthesis of a network-on-chipARTERIS INC·Filed 2019·Granted Apr 27, 2021·24 cites·8 claims
- 0496US9940423B2Editing a NoC topology on top of a floorplanARTERIS INC·Filed 2015·Granted Apr 10, 2018·23 cites·19 claims
- 0588US11836427B2Constraints and objectives used in synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2022·Granted Dec 5, 2023·1 cites·10 claims
- 0688US11601357B2System and method for generation of quality metrics for optimization tasks in topology synthesis of a networkARTERIS INC·Filed 2020·Granted Mar 7, 2023·2 cites·5 claims
- 0787US11657203B2Multi-phase topology synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2020·Granted May 23, 2023·2 cites·10 claims
- 0887US8601288B2Intelligent power controllerBRINKS RAY·Filed 2010·Granted Dec 3, 2013·36 cites·21 claims
- 0987US8438306B2Apparatus and methods for on layer concurrency in an integrated circuitDE LESCURE BENOIT·Filed 2010·Granted May 7, 2013·20 cites·19 claims
- 1086US10902166B2System and method for isolating faults in a resilient systemARTERIS INC·Filed 2018·Granted Jan 26, 2021·5 cites·8 claims
- 1184US11665776B2System and method for synthesis of a network-on-chip for deadlock-free transformationARTERIS INC·Filed 2020·Granted May 30, 2023·2 cites·19 claims
- 1283US12411801B2System and method for transaction broadcast in a network on chipARTERIS INC·Filed 2024·Granted Sep 9, 2025·0 cites·11 claims
- 1383US2025373572A1DESIGN TOOL FOR GENERATION OF DEADLOCK FREE NETWORK-ON-CHIP (NoC) WITHIN A SYSTEM-ON-CHIP (SoC)ARTERIS INC·Filed 2025·Application pending·0 cites
- 1481US2025293940A1MODIFICATION OF EXISTING NETWORK-ON-CHIPs (NoCs) USING INCREMENTAL MODIFICATIONSARTERIS INC·Filed 2025·Application pending·0 cites
- 1580US12348382B2Incremental topology modification of a network-on-chipARTERIS INC·Filed 2024·Granted Jul 1, 2025·0 cites·1 claims
- 1679US12204833B2System and method to generate a network-on-chip (NoC) description using incremental topology synthesisARTERIS INC·Filed 2023·Granted Jan 21, 2025·0 cites·11 claims
- 1779US10268794B2Editing a NoC topology on top of a floorplanARTERIS INC·Filed 2018·Granted Apr 23, 2019·2 cites·20 claims
- 1878US12135928B2Constraints and objectives used in synthesis of a network-on-chip (NoC)ARTERIS INC·Filed 2023·Granted Nov 5, 2024·0 cites·7 claims
- 1978US12067335B2Automatic configuration of pipeline modules in an electronics systemARTERIS INC·Filed 2022·Granted Aug 20, 2024·1 cites·19 claims
- 2075US12038866B2Broadcast adapters in a network-on-chipARTERIS INC·Filed 2022·Granted Jul 16, 2024·0 cites·10 claims
- 2174US10452499B2Redundancy for cache coherence systemsARTERIS INC·Filed 2018·Granted Oct 22, 2019·1 cites·16 claims
- 2274US2025233833A1SYSTEM AND METHOD FOR DEADLOCK DETECTION IN NETWORK-ON-CHIP (NoC) HAVING EXTERNAL DEPENDENCIESARTERIS INC·Filed 2025·Application pending·0 cites
- 2374US2025156616A1System and method to generate a network-on-chip topology using incremental synthesisARTERIS INC·Filed 2025·Application pending·0 cites
- 2470US11956127B2Incremental topology modification of a network-on-chipARTERIS INC·Filed 2022·Granted Apr 9, 2024·0 cites·17 claims
- 2570US11748535B2System and method to generate a network-on-chip (NoC) description using incremental topology synthesisARTERIS INC·Filed 2021·Granted Sep 5, 2023·0 cites·14 claims
- 2670US10025677B2Redundancy for cache coherence systemsARTERIS INC·Filed 2016·Granted Jul 17, 2018·1 cites·15 claims
- 2769US12438829B2System and method for deadlock detection in network-on-chip (NoC) having external dependenciesARTERIS INC·Filed 2022·Granted Oct 7, 2025·0 cites·7 claims
- 2869US11784909B2Quality metrics for optimization tasks in generation of a networkARTERIS INC·Filed 2023·Granted Oct 10, 2023·0 cites·7 claims
- 2966US11436185B2System and method for transaction broadcast in a network on chipARTERIS INC·Filed 2019·Granted Sep 6, 2022·0 cites·13 claims
- 3065US2024411969A1AUTOMATIC CONFIGURATION OF PIPELINE MODULES IN A NETWORK-ON-CHIP (NoC)ARTERIS INC·Filed 2024·Application pending·0 cites
- 3163US11416352B2System and method for logic functional redundancyARTERIS INC·Filed 2019·Granted Aug 16, 2022·0 cites·11 claims
- 3260US12380055B2System and method for performing transaction aggregation in a network-on-chip (NoC)ARTERIS INC·Filed 2021·Granted Aug 5, 2025·0 cites·9 claims
- 3360US11831557B2Switch with virtual channels for soft locking in a network-on-chip (NoC)ARTERIS INC·Filed 2022·Granted Nov 28, 2023·0 cites·18 claims
- 3460US11368402B1System and method for using soft lock with virtual channels in a network-on-chip (NoC)ARTERIS INC·Filed 2020·Granted Jun 21, 2022·0 cites·15 claims
- 3560US11176297B2Detection and isolation of faults to prevent propagation of faults in a resilient systemARTERIS INC·Filed 2020·Granted Nov 16, 2021·0 cites·9 claims
- 3659US12184499B2System and method for editing a network-on-chip (NOC)ARTERIS INC·Filed 2022·Granted Dec 31, 2024·0 cites·12 claims
- 3759US2025240355A1CONNECTIVITY SYNTHESIS OF NETWORK-ON-CHIP (NoC) IN A MULTI-PROTOCOL SYSTEM-ON-CHIP (SOC)ARTERIS INC·Filed 2025·Application pending·0 cites
- 3856US11294757B2System and method for advanced detection of failures in a network-on-chipARTERIS INC·Filed 2019·Granted Apr 5, 2022·0 cites·9 claims
- 3950US12289384B2System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)ARTERIS INC·Filed 2022·Granted Apr 29, 2025·0 cites·7 claims
- 4050US2023114760A1NETWORK-ON-CHIP (NoC) USING DEADLINE BASED ARBITRATIONARTERIS INC·Filed 2022·Application pending·0 cites
- 4148US11558259B2System and method for generating and using physical roadmaps in network synthesisARTERIS INC·Filed 2020·Granted Jan 17, 2023·0 cites·8 claims
- 4248US2023342538A1Model-driven approach for failure mode, effects, and diagnostic analysis (fmeda) automation for hardware intellectual property of complex electronic systemsARTERIS INC·Filed 2023·Application pending·0 cites
- 4342US2023101972A1SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATIONARTERIS INC·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →