Inventor · disambiguated record
Benjamin Esposito
Also filed as: ESPOSITO BENJAMIN · ESPOSITO BENJAMIN J
15 granted patents·2 pending applications·529 citations·filing 2003–2024
93Inventor score
Top patents by PatentIndex Score
17 records- 0198US6943579B1Variable fixed multipliers using memory blocksALTERA CORP·Filed 2003·Granted Sep 13, 2005·418 cites·39 claims
- 0291US10489116B1Programmable integrated circuits with multiplexer and register pipelining circuitryALTERA CORP·Filed 2014·Granted Nov 26, 2019·15 cites·13 claims
- 0389US7949699B1Implementation of decimation filter in integrated circuit device using ram-based data storageALTERA CORP·Filed 2007·Granted May 24, 2011·24 cites·19 claims
- 0483US7356554B1Variable fixed multipliers using memory blocksALTERA CORP·Filed 2005·Granted Apr 8, 2008·14 cites·37 claims
- 0582US7864080B1Sample rate conversion by controlled selection of filter outputsALTERA CORP·Filed 2008·Granted Jan 4, 2011·15 cites·19 claims
- 0677US7793013B1High-speed FIR filters in FPGAsALTERA CORP·Filed 2005·Granted Sep 7, 2010·9 cites·33 claims
- 0773US2024396579A1Systems And Methods For Electronically Scanned Array AntennasALTERA CORP·Filed 2024·Application pending·0 cites
- 0864US7932761B1Fine tuned pulse width modulationALTERA CORP·Filed 2009·Granted Apr 26, 2011·4 cites·20 claims
- 0963US7613760B1Efficient implementation of multi-channel integrators and differentiators in a programmable deviceALTERA CORP·Filed 2004·Granted Nov 3, 2009·9 cites·30 claims
- 1062US7570120B1Multichannel memory-based numerically controlled oscillatorsALTERA CORP·Filed 2007·Granted Aug 4, 2009·2 cites·20 claims
- 1162US7269617B1Hybrid multipliers implemented using DSP circuitry and programmable logic circuitryALTERA CORP·Filed 2003·Granted Sep 11, 2007·10 cites·14 claims
- 1261US7598790B1Clock synthesis using polyphase numerically controlled oscillatorALTERA CORP·Filed 2008·Granted Oct 6, 2009·2 cites·20 claims
- 1359US2020057610A1Programmable integrated circuits with multiplexer and register pipelining circuitryALTERA CORP·Filed 2019·Application pending·0 cites
- 1455US12081247B2Systems and methods for electronically scanned array antennasINTEL CORP·Filed 2019·Granted Sep 3, 2024·0 cites·20 claims
- 1553US11902132B2Analog-to-digital converter or digital-to-analog converter data path with deterministic latencyINTEL CORP·Filed 2020·Granted Feb 13, 2024·0 cites·20 claims
- 1650US7509562B1Maintaining data integrity for extended drop outs across high-speed serial linksALTERA CORP·Filed 2004·Granted Mar 24, 2009·6 cites·32 claims
- 1749US7987222B1Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extensionALTERA CORP·Filed 2004·Granted Jul 26, 2011·1 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →