Programmable integrated circuits with multiplexer and register pipelining circuitry

Abstract

An integrated circuit may have specialized processing blocks that are configurable to operate as arithmetic operators that may implement amongst others multiplication, addition, sum-of-product, and multiply-accumulation operations in a first mode. In a second mode, the specialized processing blocks may operate as multiplexers and several specialized processing blocks may be cascaded to implement wider multiplexing functions. In a third mode, the specialized processing blocks may operate as register pipelines.

What is claimed is: 
     
         1 . A circuit block, comprising:
 a digital signal processing (DSP) block input terminal configured to receive an input signal;   a multiplier having a first multiplier input terminal and a second multiplier input terminal; and   a control terminal configured to receive a control signal, wherein the first multiplier input terminal is configured to receive the input signal from the DSP block input terminal, and wherein the second multiplier input terminal is configured to receive only a selected one of a first constant value and a second constant value that is different than the first constant value depending on the polarity of the control signal.   
     
     
         2 . The circuit block of  claim 1 , wherein the first constant value is a high signal. 
     
     
         3 . The circuit block of  claim 2 , wherein the second constant value is a low signal. 
     
     
         4 . The circuit block of  claim 1 , further comprising:
 a multiplexer that is controlled by the control signal.   
     
     
         5 . The circuit block of  claim 4 , wherein the multiplexer has a first data input configured to receive the first constant value and a second data input configured to receive the second constant value. 
     
     
         6 . The circuit block of  claim 1 , further comprising:
 an adder having a first adder input terminal configured to receive signals output from the multiplier.   
     
     
         7 . The circuit block of  claim 6 , further comprising:
 an additional digital signal processing (DSP) block input terminal configured to receive an additional input signal, wherein the adder further includes a second adder input terminal operable to receive the additional input signal from the additional DSP block input terminal.   
     
     
         8 . The circuit block of  claim 6 , further comprising:
 an additional adder configured to receive signals output from the adder.   
     
     
         9 . The circuit block of  claim 6 , further comprising:
 an additional adder configured to combine signals output from the adder with other signals.   
     
     
         10 . A digital signal processing (DSP) block, comprising:
 a first digital signal processing (DSP) block input terminal configured to receive a first input signal;   a second digital signal processing (DSP) block input terminal configured to receive a second input signal;   a third digital signal processing (DSP) block input terminal configured to receive a third input signal;   a multiplier configured to receive the first and second input signals; and   an adder having a first adder input terminal configured to receive signals output from the multiplier and a second adder input terminal, wherein the third input signal can be received at the second adder input terminal but not the first adder input terminal.   
     
     
         11 . The DSP block of  claim 10 , further comprising:
 a multiplexer that is operable to receive the second input signal and that directly feeds the multiplier.   
     
     
         12 . The DSP block of  claim 10 , wherein the multiplier is further operable to receive a selected one of a first constant value and a second constant value that is different than the first constant value. 
     
     
         13 . The DSP block of  claim 12 , further comprising:
 a multiplexer configured to selectively provide either the first constant value or the second constant value to the multiplier.   
     
     
         14 . The DSP block of  claim 13 , wherein the first constant value is a high signal and wherein the second constant value is a low signal. 
     
     
         15 . A digital signal processing (DSP) block operable in a first processing mode and a second processing mode, comprising:
 first input registers configured to receive a first input signal;   second input registers configured to receive a second input signal;   a multiplier configured to receive signals from the first and second input registers;   additional registers; and   an adder configured to receive signals from the multiplier and the additional registers, wherein the additional registers output signals exhibiting a first bit width in the first processing mode and output signals exhibiting a second bit width that is different than the first bit in the second processing mode.   
     
     
         16 . The DSP block of  claim 15 , wherein the first processing mode comprises a single width mode, and wherein the second processing mode comprises a double width mode. 
     
     
         17 . The DSP block of  claim 16 , wherein the first processing mode supports register pipelining. 
     
     
         18 . The DSP block of  claim 17 , wherein the second processing mode also supports register pipelining. 
     
     
         19 . The DSP block of  claim 16 , wherein the second processing mode supports register pipelining. 
     
     
         20 . The DSP block of  claim 15 , further comprising:
 output registers that are coupled to the multiplier and that are configured to output signals having the first bit width in the first processing mode and to output signals having the second bit width in the second processing mode.