Inventor · disambiguated record
Bhushan M. Borole
Also filed as: BOROLE BHUSHAN · BOROLE BHUSHAN M
42 granted patents·8 pending applications·77 citations·filing 2017–2024
96Inventor score
Top patents by PatentIndex Score
50 records- 0196US10444817B2System, apparatus and method for increasing performance in a processor during a voltage rampINTEL CORP·Filed 2017·Granted Oct 15, 2019·8 cites·17 claims
- 0296US10430147B2Collaborative multi-user virtual realityINTEL CORP·Filed 2017·Granted Oct 1, 2019·9 cites·25 claims
- 0395US10102149B1Replacement policies for a hybrid hierarchical cacheINTEL CORP·Filed 2017·Granted Oct 16, 2018·11 cites·21 claims
- 0493US10983581B2Resource load balancing based on usage and power limitsINTEL CORP·Filed 2017·Granted Apr 20, 2021·12 cites·27 claims
- 0592US10062429B1System, apparatus and method for segmenting a memory arrayINTEL CORP·Filed 2017·Granted Aug 28, 2018·15 cites·20 claims
- 0691US11520555B2Collaborative multi-user virtual realityINTEL CORP·Filed 2021·Granted Dec 6, 2022·2 cites·20 claims
- 0791US11175719B2System, apparatus and method for increasing performance in a processor during a voltage rampINTEL CORP·Filed 2019·Granted Nov 16, 2021·3 cites·18 claims
- 0890US10747286B2Dynamic power budget allocation in multi-processor systemINTEL CORP·Filed 2018·Granted Aug 18, 2020·4 cites·22 claims
- 0985US10908865B2Collaborative multi-user virtual realityINTEL CORP·Filed 2019·Granted Feb 2, 2021·3 cites·24 claims
- 1084US2025117060A1Processor power managementINTEL CORP·Filed 2024·Application pending·0 cites
- 1183US10579121B2Processor power managementINTEL CORP·Filed 2017·Granted Mar 3, 2020·2 cites·14 claims
- 1281US12399546B2System, apparatus and method for increasing performance in a processor during a voltage rampINTEL CORP·Filed 2024·Granted Aug 26, 2025·0 cites·19 claims
- 1381US12124310B2Processor power managementINTEL CORP·Filed 2023·Granted Oct 22, 2024·0 cites·20 claims
- 1479US11080810B2Dynamically reconfigurable memory subsystem for graphics processorsINTEL CORP·Filed 2017·Granted Aug 3, 2021·2 cites·26 claims
- 1579US10409319B2System, apparatus and method for providing a local clock signal for a memory arrayINTEL CORP·Filed 2017·Granted Sep 10, 2019·2 cites·17 claims
- 1677US2024004713A1Hybrid low power homogenous grapics processing unitsINTEL CORP·Filed 2023·Application pending·0 cites
- 1776US10790010B2System, apparatus and method for segmenting a memory arrayINTEL CORP·Filed 2019·Granted Sep 29, 2020·1 cites·20 claims
- 1875US11762696B2Hybrid low power homogenous grapics processing unitsINTEL CORP·Filed 2021·Granted Sep 19, 2023·0 cites·18 claims
- 1975US11733758B2Processor power managementINTEL CORP·Filed 2021·Granted Aug 22, 2023·0 cites·17 claims
- 2074US11874715B2Dynamic power budget allocation in multi-processor systemINTEL CORP·Filed 2022·Granted Jan 16, 2024·0 cites·20 claims
- 2172US12007824B2System, apparatus and method for increasing performance in a processor during a voltage rampINTEL CORP·Filed 2021·Granted Jun 11, 2024·0 cites·19 claims
- 2271US11263720B2Frequent data value compression for graphics processing unitsINTEL CORP·Filed 2020·Granted Mar 1, 2022·0 cites·19 claims
- 2370US11176990B2System, apparatus and method for segmenting a memory arrayINTEL CORP·Filed 2020·Granted Nov 16, 2021·0 cites·20 claims
- 2469US11106264B2Processor power managementINTEL CORP·Filed 2020·Granted Aug 31, 2021·0 cites·16 claims
- 2569US10580104B2Read/write modes for reducing power consumption in graphics processing unitsINTEL CORP·Filed 2017·Granted Mar 3, 2020·1 cites·18 claims
- 2667US11263152B2Replacement policies for a hybrid hierarchical cacheINTEL CORP·Filed 2020·Granted Mar 1, 2022·0 cites·20 claims
- 2767US11169850B2Hybrid low power homogenous grapics processing unitsINTEL CORP·Filed 2019·Granted Nov 9, 2021·0 cites·18 claims
- 2867US10410699B1Multi-bit pulsed latch including serial scan chainINTEL CORP·Filed 2018·Granted Sep 10, 2019·2 cites·19 claims
- 2966US11493974B2Dynamic power budget allocation in multi-processor systemINTEL CORP·Filed 2020·Granted Nov 8, 2022·0 cites·21 claims
- 3066US2022005145A1Dynamically Reconfigurable Memory Subsystem For Graphics ProcessorsINTEL CORP·Filed 2021·Application pending·0 cites
- 3163US10817012B2System, apparatus and method for providing a local clock signal for a memory arrayINTEL CORP·Filed 2019·Granted Oct 27, 2020·0 cites·17 claims
- 3263US10691617B2Replacement policies for a hybrid hierarchical cacheINTEL CORP·Filed 2018·Granted Jun 23, 2020·0 cites·21 claims
- 3362US10748238B2Frequent data value compression for graphics processing unitsINTEL CORP·Filed 2019·Granted Aug 18, 2020·0 cites·32 claims
- 3461US2019251655A1Frequent Data Value Compression for Graphics Processing UnitsINTEL CORP·Filed 2019·Application pending·0 cites
- 3560US2021109589A1Shutting down gpu components in response to unchanged scene detectionINTEL CORP·Filed 2020·Application pending·0 cites
- 3659US10319070B2Dynamic page sizing of page table entriesINTEL CORP·Filed 2018·Granted Jun 11, 2019·0 cites·24 claims
- 3759US2025309871A1High-performance pulsed latch and clock generation for pulsed latch architecturesINTEL CORP·Filed 2024·Application pending·0 cites
- 3858US10587244B2Pulse triggered flip flopINTEL CORP·Filed 2018·Granted Mar 10, 2020·0 cites·21 claims
- 3957US10761591B2Shutting down GPU components in response to unchanged scene detectionINTEL CORP·Filed 2017·Granted Sep 1, 2020·0 cites·26 claims
- 4057US10521271B2Hybrid low power homogenous grapics processing unitsINTEL CORP·Filed 2017·Granted Dec 31, 2019·0 cites·10 claims
- 4157US10262388B2Frequent data value compression for graphics processing unitsINTEL CORP·Filed 2017·Granted Apr 16, 2019·0 cites·32 claims
- 4256US10157444B2Dynamic page sizing of page table entriesINTEL CORP·Filed 2017·Granted Dec 18, 2018·0 cites·30 claims
- 4354US10158346B2Pulse triggered flip flopINTEL CORP·Filed 2017·Granted Dec 18, 2018·0 cites·21 claims
- 4451US10901909B2Optimizing read only memory surface accessesINTEL CORP·Filed 2017·Granted Jan 26, 2021·0 cites·24 claims
- 4550US10347324B2System, apparatus and method for segmenting a memory arrayINTEL CORP·Filed 2018·Granted Jul 9, 2019·0 cites·20 claims
- 4649US10754809B2Reducing aging of register file keeper circuitsINTEL CORP·Filed 2019·Granted Aug 25, 2020·0 cites·18 claims
- 4748US10762877B2System, apparatus and method for reducing voltage swing on an interconnectINTEL CORP·Filed 2017·Granted Sep 1, 2020·0 cites·15 claims
- 4846US10324721B2Reducing aging of register file keeper circuitsINTEL CORP·Filed 2017·Granted Jun 18, 2019·0 cites·27 claims
- 4941US2018300045A1Active window rendering optimization and displayINTEL CORP·Filed 2017·Application pending·0 cites
- 5041US2018300238A1Adaptive cache sizing per workloadVEMBU BALAJI·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →