Inventor · disambiguated record
Bruce M. Fleischer
Also filed as: FLEISCHER BRUCE · FLEISCHER BRUCE M · FLEISCHER BRUCE MARTIN
76 granted patents·5 pending applications·504 citations·filing 1991–2021
99Inventor score
Top patents by PatentIndex Score
81 records- 0197US11138010B1Loop management in multi-processor dataflow architectureIBM·Filed 2020·Granted Oct 5, 2021·7 cites·20 claims
- 0296US9971713B2Multi-petascale highly efficient parallel supercomputerGLOBALFOUNDRIES INC·Filed 2015·Granted May 15, 2018·30 cites·14 claims
- 0396US9081501B2Multi-petascale highly efficient parallel supercomputerASAAD SAMEH·Filed 2011·Granted Jul 14, 2015·115 cites·41 claims
- 0496US8188761B2Soft error detection for latchesFLEISCHER BRUCE M·Filed 2011·Granted May 29, 2012·18 cites·16 claims
- 0596US7977965B1Soft error detection for latchesIBM·Filed 2010·Granted Jul 12, 2011·20 cites·14 claims
- 0694US10656913B2Enhanced low precision binary floating-point formattingIBM·Filed 2018·Granted May 19, 2020·9 cites·22 claims
- 0792US9268704B2Low latency data exchangeIBM·Filed 2013·Granted Feb 23, 2016·15 cites·17 claims
- 0891US11669489B2Sparse systolic array designIBM·Filed 2021·Granted Jun 6, 2023·2 cites·20 claims
- 0991US7865693B2Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision typeIBM·Filed 2008·Granted Jan 4, 2011·24 cites·18 claims
- 1087US9110778B2Address generation in an active memory deviceIBM·Filed 2012·Granted Aug 18, 2015·10 cites·15 claims
- 1185US11157280B2Dynamic fusion based on operand sizeIBM·Filed 2017·Granted Oct 26, 2021·4 cites·20 claims
- 1284US9298654B2Local bypass in memory computingIBM·Filed 2013·Granted Mar 29, 2016·6 cites·13 claims
- 1382US7730117B2System and method for a floating point unit with feedback prior to normalization and roundingIBM·Filed 2005·Granted Jun 1, 2010·13 cites·20 claims
- 1480US9405711B2On-chip traffic prioritization in memoryIBM·Filed 2013·Granted Aug 2, 2016·4 cites·16 claims
- 1579US11620132B2Reusing an operand received from a first-in-first-out (FIFO) buffer according to an operand specifier value specified in a predefined field of an instructionIBM·Filed 2019·Granted Apr 4, 2023·2 cites·7 claims
- 1676US9652231B2All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architectureEICHENBERGER ALEXANDRE E·Filed 2008·Granted May 16, 2017·7 cites·20 claims
- 1774US9632777B2Gather/scatter of multiple data elements with packed loading/storing into/from a register file entryFLEISCHER BRUCE M·Filed 2012·Granted Apr 25, 2017·3 cites·18 claims
- 1873US9575753B2SIMD compare instruction using permute logic for distributed register filesEICHENBERGER ALEXANDRE E·Filed 2012·Granted Feb 21, 2017·3 cites·25 claims
- 1973US9569211B2Predication in a vector processorFLEISCHER BRUCE M·Filed 2012·Granted Feb 14, 2017·4 cites·13 claims
- 2073US9389675B2Power management for in-memory computer systemsIBM·Filed 2013·Granted Jul 12, 2016·3 cites·14 claims
- 2172US10049061B2Active memory device gather, scatter, and filterIBM·Filed 2012·Granted Aug 14, 2018·3 cites·14 claims
- 2272US9405712B2On-chip traffic prioritization in memoryIBM·Filed 2013·Granted Aug 2, 2016·2 cites·16 claims
- 2372US9088279B2Margin improvement for configurable local clock bufferIBM·Filed 2013·Granted Jul 21, 2015·3 cites·17 claims
- 2472US6131182AMethod and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macrosIBM·Filed 1997·Granted Oct 10, 2000·72 cites·31 claims
- 2571US11095313B2Employing single error correction and triple error detection to optimize bandwidth and resilience under multiple bit failuresIBM·Filed 2019·Granted Aug 17, 2021·2 cites·15 claims
- 2671US9841926B2On-chip traffic prioritization in memoryIBM·Filed 2016·Granted Dec 12, 2017·1 cites·20 claims
- 2770US10838868B2Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory componentsIBM·Filed 2019·Granted Nov 17, 2020·1 cites·21 claims
- 2870US10572263B2Executing a composite VLIW instruction having a scalar atom that indicates an iteration of executionIBM·Filed 2016·Granted Feb 25, 2020·1 cites·21 claims
- 2970US9575756B2Predication in a vector processorFLEISCHER BRUCE M·Filed 2012·Granted Feb 21, 2017·2 cites·13 claims
- 3068US5748012AMethodology to test pulsed logic circuits in pseudo-static modeIBM·Filed 1996·Granted May 5, 1998·23 cites·15 claims
- 3167US6842765B2Processor design for extended-precision arithmeticIBM·Filed 2001·Granted Jan 11, 2005·13 cites·15 claims
- 3266US7739323B2Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generatorIBM·Filed 2006·Granted Jun 15, 2010·3 cites·25 claims
- 3366US7721171B2Scheme to optimize scan chain ordering in designsIBM·Filed 2007·Granted May 18, 2010·5 cites·9 claims
- 3465US9274971B2Low latency data exchangeIBM·Filed 2012·Granted Mar 1, 2016·1 cites·17 claims
- 3565US8990620B2Exposed-pipeline processing element with rollbackIBM·Filed 2012·Granted Mar 24, 2015·1 cites·19 claims
- 3664US9582466B2Vector register fileFLEISCHER BRUCE M·Filed 2012·Granted Feb 28, 2017·1 cites·17 claims
- 3763US9329664B2Power management for a computer systemIBM·Filed 2013·Granted May 3, 2016·1 cites·10 claims
- 3862US8560924B2Register file soft error recoveryFLEISCHER BRUCE M·Filed 2010·Granted Oct 15, 2013·1 cites·18 claims
- 3961US12182576B2Executing a composite scalar-vector VLIW instruction having a repeat fieldIBM·Filed 2019·Granted Dec 31, 2024·0 cites·19 claims
- 4061US8656332B2Automated critical area allocation in a physical synthesized hierarchical designFLEISCHER BRUCE M·Filed 2009·Granted Feb 18, 2014·2 cites·20 claims
- 4160US11775257B2Enhanced low precision binary floating-point formattingIBM·Filed 2020·Granted Oct 3, 2023·0 cites·20 claims
- 4257US11182127B2Binary floating-point multiply and scale operation for compute-intensive numerical applications and apparatusesIBM·Filed 2019·Granted Nov 23, 2021·0 cites·17 claims
- 4356US11347517B2Reduced precision based programmable and SIMD dataflow architectureIBM·Filed 2019·Granted May 31, 2022·0 cites·20 claims
- 4456US11281745B2Half-precision floating-point arrays at low overheadIBM·Filed 2019·Granted Mar 22, 2022·0 cites·20 claims
- 4556US5191240ABicmos driver circuits with improved low output levelIBM·Filed 1991·Granted Mar 2, 1993·12 cites·5 claims
- 4655US11314482B2Low latency floating-point division operationsIBM·Filed 2019·Granted Apr 26, 2022·0 cites·20 claims
- 4755US9400656B2Chaining between exposed vector pipelinesIBM·Filed 2013·Granted Jul 26, 2016·0 cites·12 claims
- 4855US5751619ARecurrent adrithmetical computation using carry-save arithmeticIBM·Filed 1996·Granted May 12, 1998·29 cites·5 claims
- 4954US9910802B2High bandwidth low latency data exchange between processing elementsIBM·Filed 2015·Granted Mar 6, 2018·0 cites·6 claims
- 5054US9104465B2Main processor support of tasks performed in memoryIBM·Filed 2012·Granted Aug 11, 2015·0 cites·20 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →