Inventor · disambiguated record
Bruce Millar
Also filed as: MILLAR BRUCE
38 granted patents·7 pending applications·2,109 citations·filing 1994–2020
98Inventor score
Files withMOSAID TECHNOLOGIES INC29CONVERSANT INTELLECTUAL PROPERTY MAN INC5ADVANCED MEMORY INTERNATIONAL3GILLINGHAM PETER2PYEON HONG BEOM2
Top patents by PatentIndex Score
45 records- 0199US6510503B2High bandwidth memory interfaceMOSAID TECHNOLOGIES INC·Filed 1998·Granted Jan 21, 2003·445 cites·30 claims
- 0298US6442644B1Memory system having synchronous-link DRAM (SLDRAM) devices and controllerADVANCED MEMORY INTERNATIONAL·Filed 1998·Granted Aug 27, 2002·551 cites·40 claims
- 0398US6337590B1Digital delay locked loopMOSAID TECHNOLOGIES INC·Filed 2000·Granted Jan 8, 2002·118 cites·25 claims
- 0497US6779097B2High bandwidth memory interfaceMOSAID TECHNOLOGIES INC·Filed 2002·Granted Aug 17, 2004·90 cites·10 claims
- 0597US6087868ADigital delay locked loopMOSAID TECHNOLOGIES INC·Filed 1998·Granted Jul 11, 2000·147 cites·10 claims
- 0697US5917760ADe-skewing data signals in a memory systemSLDRAM INC·Filed 1997·Granted Jun 29, 1999·324 cites·7 claims
- 0796US7299330B2High bandwidth memory interfaceMOSAID TECHNOLOGIES INC·Filed 2004·Granted Nov 20, 2007·74 cites·27 claims
- 0891US8035413B2Dynamic impedance control for input/output buffersMOSAID TECHNOLOGIES INC·Filed 2010·Granted Oct 11, 2011·10 cites·34 claims
- 0991US7834654B2Dynamic impedance control for input/output buffersMOSAID TECHNOLOGIES INC·Filed 2008·Granted Nov 16, 2010·18 cites·31 claims
- 1090US8654573B2High bandwidth memory interfaceMOSAID TECHNOLOGIES INC·Filed 2013·Granted Feb 18, 2014·7 cites·8 claims
- 1188US5945886AHigh-speed bus structure for printed circuit boardsSLDRAM INC·Filed 1997·Granted Aug 31, 1999·75 cites·16 claims
- 1286US7889580B2Memory system having incorrupted strobe signalsMOSAID TECHNOLOGIES INC·Filed 2010·Granted Feb 15, 2011·7 cites·7 claims
- 1384US5870049ACurrent mode digital to analog converterMOSAID TECHNOLOGIES INC·Filed 1997·Granted Feb 9, 1999·80 cites·28 claims
- 1483US7761831B2ASIC design using clock and power grid standard cellMOSAID TECHNOLOGIES INC·Filed 2005·Granted Jul 20, 2010·17 cites·22 claims
- 1580US7652932B2Memory system having incorrupted strobe signalsMOSAID TECHNOLOGIES INC·Filed 2007·Granted Jan 26, 2010·8 cites·6 claims
- 1679US8013646B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2010·Granted Sep 6, 2011·2 cites·30 claims
- 1778US7129760B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2005·Granted Oct 31, 2006·6 cites·2 claims
- 1875US7551012B2Phase shifting in DLL/PLLMOSAID TECHNOLOGIES INC·Filed 2007·Granted Jun 23, 2009·9 cites·18 claims
- 1974US8250297B2High bandwidth memory interfaceGILLINGHAM PETER·Filed 2007·Granted Aug 21, 2012·3 cites·42 claims
- 2074US7391247B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2006·Granted Jun 24, 2008·4 cites·11 claims
- 2174US5497115AFlip-flop circuit having low standby power for driving synchronous dynamic random access memoryMOSAID TECHNOLOGIES INC·Filed 1994·Granted Mar 5, 1996·34 cites·6 claims
- 2273US5652733ACommand encoded delayed clock generatorMOSAID TECHNOLOGIES INC·Filed 1996·Granted Jul 29, 1997·32 cites·7 claims
- 2372US7248531B2Voltage down converter for high speed memoryMOSAID TECHNOLOGIES INC·Filed 2005·Granted Jul 24, 2007·5 cites·9 claims
- 2470US8266372B2High bandwidth memory interfaceGILLINGHAM PETER·Filed 2007·Granted Sep 11, 2012·2 cites·43 claims
- 2570US7671650B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2008·Granted Mar 2, 2010·3 cites·14 claims
- 2670US6853231B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2003·Granted Feb 8, 2005·8 cites·14 claims
- 2769US8847623B2Dynamic impedance control for input/output buffersMILLAR BRUCE·Filed 2011·Granted Sep 30, 2014·3 cites·21 claims
- 2869US7593281B2Voltage down converter for high speed memoryMOSAID TECHNOLOGIES INC·Filed 2007·Granted Sep 22, 2009·4 cites·7 claims
- 2966US7863954B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2010·Granted Jan 4, 2011·1 cites·13 claims
- 3065US7765376B2Apparatuses for synchronous transfer of informationMOSAID TECHNOLOGIES INC·Filed 2007·Granted Jul 27, 2010·1 cites·27 claims
- 3162US10985757B2Dynamic impedance control for input/output buffersCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2020·Granted Apr 20, 2021·0 cites·7 claims
- 3262US2015078057A1High bandwidth memory interfaceCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2014·Application pending·0 cites
- 3360US7038517B2Timing vernier using a delay locked loopMOSAID TECHNOLOGIES INC·Filed 2005·Granted May 2, 2006·2 cites·20 claims
- 3460US2013329482A1High bandwidth memory interfaceMOSAID TECHNOLOGIES INC·Filed 2013·Application pending·0 cites
- 3559US5633607AEdge triggered set-reset flip-flop (SRFF)MOSAID TECHNOLOGIES INC·Filed 1995·Granted May 27, 1997·16 cites·6 claims
- 3654US2010268906A1High bandwidth memory interfaceMOSAID TECHNOLOGIES INC·Filed 2010·Application pending·0 cites
- 3753US2016277027A1Dynamic impedance control for input/output buffersCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2016·Application pending·0 cites
- 3852US10608634B2Dynamic impedance control for input/output buffersCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2017·Granted Mar 31, 2020·0 cites·7 claims
- 3951US9300291B2Dynamic impedance control for input/output buffersCONVERSANT INTELLECTUAL PROPERTY MAN INC·Filed 2014·Granted Mar 29, 2016·0 cites·16 claims
- 4049US2014071781A1Voltage down converter for high speed memoryMOSAID TECHNOLOGIES INC·Filed 2013·Application pending·0 cites
- 4147US8611171B2Voltage down converter for high speed memoryPYEON HONG BEOM·Filed 2012·Granted Dec 17, 2013·0 cites·8 claims
- 4245US8164968B2Voltage down converter for high speed memoryPYEON HONG BEOM·Filed 2009·Granted Apr 24, 2012·0 cites·8 claims
- 4340US2003126356A1Memory system having synchronous-link DRAM (SLDRAM) devices and controllerADVANCED MEMORY INTERNATIONAL·Filed 2002·Application pending·0 cites
- 4434US6249827B1Method for transferring data associated with a read/write command between a processor and a reader circuit using a plurality of clock linesADVANCED MEMORY INTERNATIONAL·Filed 1997·Granted Jun 19, 2001·3 cites·26 claims
- 4533US2002041196A1Delay locked loopFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →