Memory system having synchronous-link DRAM (SLDRAM) devices and controller

Abstract

A SLDRAM System is provided with a plurality of in-circuit, calibratable memory modules and a memory controller for issuing unicast and multicast command packets to the memory modules. Command packets are transmitted over a unidirectional command link that includes a complementary pair of command clock lines, a command FLAG line and a plurality of noncomplemented command bit lines. Each of the command clock lines, command bit lines and the FLAG line is a SLIO transmission line. Data transfer operations are carried out in response to the command packets over one or more bidirectional data links that each includes two complementary pairs of data clock lines, and a plurality of noncomplemented data bit lines. Each of the data clock lines and the data bit lines is a SLIO transmission line. Each SLIO transmission line is single-end terminated and preferably tapped into by way of stub resistors.

What is claimed is:  
     
         1 . A memory module [ 110 ] for use in a memory system [ 100 ] having a command link [ 151 ] and one or more data links [ 155 , 156 ] where the command link includes a first pair of lines [ 151   b ] for carrying complementary, command clock signals [CCLK/CCLK#], where each data link includes a second pair of lines [ 155   b ] for carrying complementary, first data clock signals [DCLK0/0#], and where each data link further includes a third pair of lines [ 155   c ] for carrying complementary, second data clock signals [DCLK1/1#], said memory module comprising: 
 a series of interconnect pins [ 400 ] extending between opposed first and second interconnect extremes [pins — 1:64] wherein said series of interconnect pins includes: 
 (a) a first pair of interconnect pins [28,29] for receiving said complementary, command clock signals [CCLK/CCLK#] 
 (b) a second pair of interconnect pins [24,25] for transceiving said complementary, first data clock signals [DCLK0/0#] of a first data link, where the second pair of interconnect pins are located substantially adjacent to the first pair of interconnect pins; and  
 (c) a third pair of interconnect pins [26,27] for transceiving said complementary, second data clock signals [DLK1/1#] of the first data link, where the third pair of interconnect pins are located substantially adjacent to the first pair of interconnect pins.  
   
     
     
         2 . A memory module [ 110 ] according to  claim 1  wherein: 
 (a.1) the first pair of interconnect pins are located substantially centrally within the series of interconnect pins.  
 
     
     
         3 . A memory module [ 110 ] according to  claim 1  for use in said system [ 100 ], wherein a first data link of the system further includes a first plurality of data lines [ 155   a ] each for carrying a noncomplemented data signal [DQ(i)], wherein said series of interconnect pins further includes: 
 (d) a first plurality of noncomplemented interconnect pins of a same number as said first plurality of data lines, the first plurality of noncomplemented interconnect pins [ 417 , 450 ] being distributed in a substantially symmetric fashion about each of said first, second and third pairs of interconnect pins [ 427 ].  
 
     
     
         4 . A memory module [ 110 ] according to  claim 3  for use in said system [ 110 ], wherein the command link of the system further includes a second plurality of command lines [ 151   a ] each for carrying a noncomplemented command signal [CA(j)], wherein said series of interconnect pins further includes: 
 (e) a second plurality of noncomplemented interconnect pins of a same number as said second plurality of command lines, the second plurality of noncomplemented interconnect pins [ 430 ] being disposed substantially adjacent to the combination [ 427 ] of said first, second and third pairs of interconnect pins.  
 
     
     
         5 . A Synchronous-Link Dynamic Random Access Memory (SLDRAM) System [ 100 ] comprising: 
 (a) a command module [ 150 ] for issuing unicast command packets [ 210 ] directed to uniquely addressable ones of plural memory units [ 111 , 211 ] and for issuing multicast command packets directed to addressable collections of said memory units;    (b) a command link [ 151 ] for carrying the command packets;    (c) one or more data links [ 155 , 156 ] for carrying data corresponding to packet-commanded data-transfer actions; and    (d) one or more, in-circuit programmably-calibratable SLDRAM modules [ 110 - 180 ] each having one or more of said addressable memory units, where each SLDRAM module is capable of interfacing with the command link and at least one of the data links for appropriately responding to informational queries provided by command packets, for further appropriately responding to tuning (adjustment, or calibrating) commands provided by command packets, and for yet further appropriately responding to data addressing and other data-transfer-related commands provided by command packets.    
     
     
         6 . A method for initializing a SLDRAM system [ 100 ] having one or more, in-circuit programmably-calibratable SLDRAM modules [ 110 - 180 ], said method comprising the steps of: 
 (a) first initializing the SLDRAM system by broadcasting from a reference location [ 150 ] a predefined first synchronization sequence over command/address lines [CA(9:0)] and data lines [DQ(17:0)] of the system while simultaneously and synchronously outputting from the reference location a continuously-running clock train over one or more clock lines [CCLK,DCLK0,DCLK1] of the system for allowing one or more SLDRAM modules present in the system to each self-adjust local command-receiving circuits [ 117 ] and data-receiving [ 115 ] circuits of the SLDRAM module to synchronously recognize the predefined first synchronization sequence at the locality of the SLDRAM module;    (b) second initializing the SLDRAM system by sequentially assigning identification codes [ID's] to individually-addressable, memory units [ 111 , 121 ] within the in-system SLDRAM modules;    (c) third initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to adjust output levels of the SLDRAM module's data-clock driving circuits [ 118 ] and data-line driving circuits [ 116 ] to levels acceptable to an in-circuit memory controller [ 150 ];    (d) fourth initializing the SLDRAM system by sequentially commanding each in-circuit SLDRAM module to respectively output a predefined second synchronization sequence over the data lines [DQ(17:0)] of the system while simultaneously and synchronously outputting from the commanded SLDRAM module, a continuously-running clock train over one or more data-clock lines [DCLK0,DCLK1] of the system, this for allowing the in-circuit memory controller to command adjustments (e.g., individual phase changes) to local data-outputting circuits [ 116 ] and local data-clock outputting circuits [ 118 ] of the sequence-outputting SLDRAM module so that the memory controller will be able to synchronously recognize the predefined second synchronization sequence at the locality of the memory controller; and    (e) fifth initializing the SLDRAM system by sequentially determining data read and data write latency times of respective ones of the in-circuit, individually-addressable, memory units.    
     
     
         7 . A method for using a SLDRAM system [ 100 ] having one or more, in-circuit programmably-calibratable SLDRAM modules [ 110 - 180 ], said method comprising the steps of: 
 (a) synchronously issuing command packets from a reference location [ 150 ] of the SLDRAM system using command/address lines [CA(9:0)] of the system and command-clock lines [CCLK/CCLK#] of the system for transmitting the command packets to one or more of the in-circuit-calibratable SLDRAM modules of the system, where first ones of the issued command packets individually or collectively address one or more individually-addressable, memory units within the SLDRAM modules and define a data-transfer operation to be carried out by the individually or collectively addressed memory units; and    (b) causing the addressed memory units to responsively perform the defined data-transfer operation within a time slot that follows receipt by the memory unit of a respective command packet, where latency between the receipt of the respective command packet and the responsive performance the defined data-transfer operation is adjustable; and    (c) wherein second ones of the issued command packets individually address one or more of the individually-addressable, memory units and define one or more respective data-transfer latencies for the individually-addressed memory unit.