Inventor · disambiguated record
Henry Stracovsky
Also filed as: STRACOVSKY HENRY
26 granted patents·3 pending applications·1,272 citations·filing 1998–2024
97Inventor score
Files withINFINEON TECHNOLOGIES AG11RAMBUS INC10ADVANCED MEMORY INTERNATIONAL2INFINEION TECHNOLOGIES AG1INFINEON AG1
Top patents by PatentIndex Score
29 records- 0198US9043674B2Error detection and correction apparatus and methodINTEL CORP·Filed 2012·Granted May 26, 2015·71 cites·24 claims
- 0298US6442644B1Memory system having synchronous-link DRAM (SLDRAM) devices and controllerADVANCED MEMORY INTERNATIONAL·Filed 1998·Granted Aug 27, 2002·551 cites·40 claims
- 0396US11294830B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2020·Granted Apr 5, 2022·8 cites·18 claims
- 0490US6442666B1Techniques for improving memory access in a virtual memory systemINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 27, 2002·71 cites·8 claims
- 0588US10613995B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2016·Granted Apr 7, 2020·7 cites·18 claims
- 0688US6216178B1Methods and apparatus for detecting the collision of data on a data bus in case of out-of-order memory accesses of different times of memory access executionINFINEON TECHNOLOGIES AG·Filed 1999·Granted Apr 10, 2001·137 cites·8 claims
- 0787US11768780B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2022·Granted Sep 26, 2023·1 cites·20 claims
- 0885US6587894B1Apparatus for detecting data collision on data bus for out-of-order memory accesses with access execution time based in part on characterization data specific to memoryINFINEON TECHNOLOGIES AG·Filed 2000·Granted Jul 1, 2003·41 cites·10 claims
- 0984US10169258B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2016·Granted Jan 1, 2019·3 cites·17 claims
- 1084US6430642B1Methods and apparatus for prioritization of access to external devicesINFINEON TECHNOLOGIES AG·Filed 2000·Granted Aug 6, 2002·34 cites·10 claims
- 1181US2025110897A1Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2024·Application pending·0 cites
- 1278US12141081B2Training and operations with a double buffered memory topologyRAMBUS INC·Filed 2023·Granted Nov 12, 2024·0 cites·20 claims
- 1377US11907139B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2022·Granted Feb 20, 2024·0 cites·18 claims
- 1477US6195724B1Methods and apparatus for prioritization of access to external devicesINFINEON TECHNOLOGIES AG·Filed 1999·Granted Feb 27, 2001·70 cites·11 claims
- 1571US11537540B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2021·Granted Dec 27, 2022·0 cites·20 claims
- 1671US6510474B1Methods and apparatus for re-reordering command and data packets in order to restore an original order of out-of-order memory requestsINFINEON TECHNOLOGIES AG·Filed 1999·Granted Jan 21, 2003·62 cites·7 claims
- 1768US11003601B2Memory system design using buffer(s) on a mother boardRAMBUS INC·Filed 2020·Granted May 11, 2021·0 cites·20 claims
- 1864US10614002B2Memory system design using buffer(S) on a mother boardRAMBUS INC·Filed 2018·Granted Apr 7, 2020·0 cites·20 claims
- 1960US6378049B1Universal memory controllerINFINEON TECHNOLOGIES AG·Filed 1999·Granted Apr 23, 2002·37 cites·16 claims
- 2058US12455799B2Explicit lockstep for functional safetyQUALCOMM INC·Filed 2023·Granted Oct 28, 2025·0 cites·18 claims
- 2157US6286075B1Method of speeding up access to a memory page using a number of M page tag registers to track a state of physical pages in a memory device having N memory banks where N is greater than MINFINEON TECHNOLOGIES AG·Filed 1999·Granted Sep 4, 2001·34 cites·12 claims
- 2256US8495464B2Reliability support in memory systems without error correcting code supportSTRACOVSKY HENRY·Filed 2010·Granted Jul 23, 2013·1 cites·14 claims
- 2356US6532505B1Universal resource access controllerINFINEON TECHNOLOGIES AG·Filed 1999·Granted Mar 11, 2003·30 cites·18 claims
- 2456US6374323B1Computer memory conflict avoidance using page registersINFINEON TECHNOLOGIES AG·Filed 1999·Granted Apr 16, 2002·32 cites·3 claims
- 2555US6385708B1Using a timing-look-up-table and page timers to determine the time between two consecutive memory accessesINFINEON TECHNOLOGIES AG·Filed 1999·Granted May 7, 2002·29 cites·14 claims
- 2652US6453370B1Using of bank tag registers to avoid a background operation collision in memory systemsINFINEION TECHNOLOGIES AG·Filed 1999·Granted Sep 17, 2002·31 cites·14 claims
- 2749US6539440B1Methods and apparatus for prediction of the time between two consecutive memory accessesINFINEON AG·Filed 1999·Granted Mar 25, 2003·22 cites·13 claims
- 2840US2003126356A1Memory system having synchronous-link DRAM (SLDRAM) devices and controllerADVANCED MEMORY INTERNATIONAL·Filed 2002·Application pending·0 cites
- 2933US2014089755A1Reliability enhancements for high speed memory - parity protection on command/address and ecc protection on dataKANTAMSETTI SHVETA·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →