Inventor · disambiguated record
Brett Allen Neal
Also filed as: NEAL BRETT · NEAL BRETT A · NEAL BRETT ALLEN
14 granted patents·70 citations·filing 2003–2018
91Inventor score
Top patents by PatentIndex Score
14 records- 0184US10643018B1System and method for determining return path quality in an electrical circuitCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted May 5, 2020·4 cites·16 claims
- 0282US8910105B1Routing processCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Dec 9, 2014·7 cites·20 claims
- 0382US8464196B1Method and system for routing optimally between terminals through intermediate vias in a circuit designLAWSON RANDALL SCOTT·Filed 2012·Granted Jun 11, 2013·9 cites·9 claims
- 0477US8904332B1Display processCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Dec 2, 2014·5 cites·17 claims
- 0573US10445459B1Interactive routing with poly viasCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Oct 15, 2019·3 cites·19 claims
- 0673US10409934B1System, method, and computer program product for static and dynamic phase matching in an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Sep 10, 2019·4 cites·8 claims
- 0772US9990456B1Routing process including dynamically changing pad sizesCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Jun 5, 2018·2 cites·10 claims
- 0871US8479138B1Global constraint optimizationLAWSON RANDALL SCOTT·Filed 2009·Granted Jul 2, 2013·6 cites·37 claims
- 0971US7100135B2Method and system to evaluate signal line spacingINTEL CORP·Filed 2004·Granted Aug 29, 2006·15 cites·7 claims
- 1070US9202001B1System and method for electronic design routing between terminalsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Dec 1, 2015·3 cites·21 claims
- 1167US8726222B1Method and system for routing optimally between terminals through intermediate vias in a circuit designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 13, 2014·2 cites·17 claims
- 1262US7421673B2Design checks for signal linesINTEL CORP·Filed 2006·Granted Sep 2, 2008·2 cites·8 claims
- 1359US7111270B2Method and apparatus to adaptively validate a physical net routing topology of a substrate designINTEL CORP·Filed 2003·Granted Sep 19, 2006·8 cites·28 claims
- 1448US7421672B2Checks for signal linesINTEL CORP·Filed 2006·Granted Sep 2, 2008·0 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →