Inventor · disambiguated record
Brian Reed
Also filed as: REED BRIAN · REED BRIAN WILLIAM
8 granted patents·2 pending applications·251 citations·filing 2003–2017
87Inventor score
Files withTELA INNOVATIONS INC3REED BRIAN2ADVANCED RISC MACH LTD1ARM PHYSICAL IP INC1ARTISAN COMPONENTS INC1
Top patents by PatentIndex Score
10 records- 0197US8448102B2Optimizing layout of irregular structures in regular layout contextKORNACHUK STEPHEN·Filed 2009·Granted May 21, 2013·105 cites·26 claims
- 0296US8225239B2Methods for defining and utilizing sub-resolution features in linear topologyREED BRIAN·Filed 2009·Granted Jul 17, 2012·117 cites·25 claims
- 0387US9754878B2Semiconductor chip including a chip level based on a layout that includes both regular and irregular wiresTELA INNOVATIONS INC·Filed 2013·Granted Sep 5, 2017·7 cites·22 claims
- 0484US9122832B2Methods for controlling microloading variation in semiconductor wafer layout and fabricationREED BRIAN·Filed 2009·Granted Sep 1, 2015·12 cites·20 claims
- 0562US8680912B2Level shifting circuitryREED BRIAN WILLIAM·Filed 2012·Granted Mar 25, 2014·3 cites·15 claims
- 0652US2017365548A1Optimizing Layout of Irregular Structures in Regular Layout ContextTELA INNOVATIONS INC·Filed 2017·Application pending·0 cites
- 0749US7005910B2Feed-forward circuit for reducing delay through an input bufferARM PHYSICAL IP INC·Filed 2004·Granted Feb 28, 2006·6 cites·2 claims
- 0849US2015363542A1Methods for Controlling Microloading Variation in Semiconductor Wafer Layout and FabricationTELA INNOVATIONS INC·Filed 2015·Application pending·0 cites
- 0937US6924687B2Voltage tolerant circuit for protecting an input bufferARTISAN COMPONENTS INC·Filed 2003·Granted Aug 2, 2005·1 cites·11 claims
- 1035US9070431B2Memory circuitry with write assistADVANCED RISC MACH LTD·Filed 2013·Granted Jun 30, 2015·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →