Inventor · disambiguated record
Brian L. Tessier
Also filed as: TESSIER BRIAN · TESSIER BRIAN L
14 granted patents·6 pending applications·229 citations·filing 2002–2016
92Inventor score
Top patents by PatentIndex Score
20 records- 0195US6900519B2Diffused extrinsic base and method for fabricationIBM·Filed 2004·Granted May 31, 2005·95 cites·17 claims
- 0292US6774000B2Method of manufacture of MOSFET device with in-situ doped, raised source and drain structuresIBM·Filed 2002·Granted Aug 10, 2004·56 cites·17 claims
- 0390US7244644B2Undercut and residual spacer prevention for dual stressed layersADVANCED MICRO DEVICES INC·Filed 2005·Granted Jul 17, 2007·19 cites·20 claims
- 0483US6858903B2MOSFET device with in-situ doped, raised source and drain structuresIBM·Filed 2004·Granted Feb 22, 2005·24 cites·21 claims
- 0582US7459382B2Field effect device with reduced thickness gateIBM·Filed 2006·Granted Dec 2, 2008·9 cites·1 claims
- 0677US7888738B2Method of forming a guard ring or contact to an SOI substrateIBM·Filed 2010·Granted Feb 15, 2011·5 cites·9 claims
- 0772US7358172B2Poly filled substrate contact on SOI structureIBM·Filed 2006·Granted Apr 15, 2008·4 cites·18 claims
- 0871US7718514B2Method of forming a guard ring or contact to an SOI substrateIBM·Filed 2007·Granted May 18, 2010·5 cites·9 claims
- 0961US7776695B2Semiconductor device structure having low and high performance devices of same conductive type on same substrateIBM·Filed 2006·Granted Aug 17, 2010·2 cites·17 claims
- 1057US7485521B2Self-aligned dual stressed layers for NFET and PFETIBM·Filed 2005·Granted Feb 3, 2009·5 cites·19 claims
- 1154US6869854B2Diffused extrinsic base and method for fabricationIBM·Filed 2002·Granted Mar 22, 2005·5 cites·29 claims
- 1251US7592245B2Poly filled substrate contact on SOI structureIBM·Filed 2008·Granted Sep 22, 2009·0 cites·9 claims
- 1349US2009311855A1Method of fabricating a gate structureBRUFF RICHARD A·Filed 2009·Application pending·0 cites
- 1449US2008286916A1Methods of stressing transistor channel with replaced gateLUO ZHIJIONG·Filed 2008·Application pending·0 cites
- 1547US2009101980A1Method of fabricating a gate structure and the structure thereofIBM·Filed 2007·Application pending·0 cites
- 1646US2007281405A1Methods of stressing transistor channel with replaced gate and related structuresIBM·Filed 2006·Application pending·0 cites
- 1745US8492803B2Field effect device with reduced thickness gateAMOS RICKY S·Filed 2008·Granted Jul 23, 2013·0 cites·16 claims
- 1841US2008173942A1STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDEIBM·Filed 2007·Application pending·0 cites
- 1935US2005275034A1A manufacturable method and structure for double spacer cmos with optimized nfet/pfet performanceIBM·Filed 2004·Application pending·0 cites
- 2033US10224414B2Method for providing a low-k spacerLAM RES CORP·Filed 2016·Granted Mar 5, 2019·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →