Inventor · disambiguated record
Carlos Mazure
Also filed as: MAZURE CARLOS · MAZURE CARLOS A
81 granted patents·9 pending applications·3,435 citations·filing 1990–2014
99Inventor score
Files withSOITEC SILICON ON INSULATOR30MOTOROLA INC26MAZURE CARLOS14LETERTRE FABRICE3BOURDELLE KONSTANTIN2
Top patents by PatentIndex Score
90 records- 0199US5308782ASemiconductor memory device and method of formationMOTOROLA INC·Filed 1992·Granted May 3, 1994·461 cites·22 claims
- 0297US5414289ADynamic memory device having a vertical transistorMOTOROLA INC·Filed 1993·Granted May 9, 1995·131 cites·30 claims
- 0396US8305803B2DRAM memory cell having a vertical bipolar injectorMAZURE CARLOS·Filed 2010·Granted Nov 6, 2012·27 cites·20 claims
- 0496US5308778AMethod of formation of transistor and logic gatesMOTOROLA INC·Filed 1993·Granted May 3, 1994·128 cites·33 claims
- 0596US5308788ATemperature controlled process for the epitaxial growth of a film of materialMOTOROLA INC·Filed 1993·Granted May 3, 1994·330 cites·30 claims
- 0695US6955971B2Semiconductor structure and methods for fabricating sameSOITEC SILICON ON INSULATOR·Filed 2003·Granted Oct 18, 2005·92 cites·39 claims
- 0795US5627395AVertical transistor structureMOTOROLA INC·Filed 1995·Granted May 6, 1997·114 cites·20 claims
- 0895US5414288AVertical transistor having an underlying gate electrode contactMOTOROLA INC·Filed 1994·Granted May 9, 1995·114 cites·7 claims
- 0995US5340754AMethod for forming a transistor having a dynamic connection between a substrate and a channel regionMOTOROLA INC·Filed 1992·Granted Aug 23, 1994·92 cites·20 claims
- 1094US5612563AVertically stacked vertical transistors used to form vertical logic gate structuresMOTOROLA INC·Filed 1994·Granted Mar 18, 1997·170 cites·40 claims
- 1194US5578850AVertically oriented DRAM structureMOTOROLA INC·Filed 1996·Granted Nov 26, 1996·98 cites·35 claims
- 1294US5291438ATransistor and a capacitor used for forming a vertically stacked dynamic random access memory cellMOTOROLA INC·Filed 1993·Granted Mar 1, 1994·91 cites·21 claims
- 1393US7785995B2Semiconductor buffer structuresASM INC·Filed 2006·Granted Aug 31, 2010·16 cites·33 claims
- 1493US7018909B2Forming structures that include a relaxed or pseudo-relaxed layer on a substrateSOITEC SILICON ON INSULATOR·Filed 2004·Granted Mar 28, 2006·51 cites·31 claims
- 1593US5398200AVertically formed semiconductor random access memory deviceMOTOROLA INC·Filed 1994·Granted Mar 14, 1995·160 cites·31 claims
- 1693US5219793AMethod for forming pitch independent contacts and a semiconductor device having the sameMOTOROLA INC·Filed 1991·Granted Jun 15, 1993·149 cites·24 claims
- 1792US8652887B2Multi-layer structures and process for fabricating semiconductor devicesNGUYEN BICH-YEN·Filed 2012·Granted Feb 18, 2014·14 cites·20 claims
- 1892US5324673AMethod of formation of vertical transistorMOTOROLA INC·Filed 1992·Granted Jun 28, 1994·86 cites·21 claims
- 1992US5314834AField effect transistor having a gate dielectric with variable thicknessMOTOROLA INC·Filed 1991·Granted May 24, 1994·99 cites·5 claims
- 2091US7407867B2Method for concurrently producing at least a pair of semiconductor structures that each include at least one useful layer on a substrateSOITEC SILICON ON INSULATOR·Filed 2006·Granted Aug 5, 2008·19 cites·14 claims
- 2191US5451538AMethod for forming a vertically integrated dynamic memory cellMOTOROLA INC·Filed 1994·Granted Sep 19, 1995·69 cites·19 claims
- 2289US8575697B2SRAM-type memory cellMAZURE CARLOS·Filed 2011·Granted Nov 5, 2013·13 cites·12 claims
- 2387US8384425B2Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrateSOITEC SILICON ON INSULATOR·Filed 2010·Granted Feb 26, 2013·9 cites·18 claims
- 2487US7736988B2Forming structures that include a relaxed or pseudo-relaxed layer on a substrateSOITEC SILICON ON INSULATOR·Filed 2006·Granted Jun 15, 2010·9 cites·10 claims
- 2587US7670929B2Method for direct bonding two semiconductor substratesSOITEC SILICON ON INSULATOR·Filed 2007·Granted Mar 2, 2010·12 cites·18 claims
- 2687US6964914B2Method of manufacturing a free-standing substrate made of monocrystalline semi-conductor materialSOITEC SILICON ON INSULATOR·Filed 2003·Granted Nov 15, 2005·44 cites·23 claims
- 2786US7575988B2Method of fabricating a hybrid substrateSOITEC SILICON ON INSULATOR·Filed 2007·Granted Aug 18, 2009·14 cites·13 claims
- 2886US5210435AITLDD transistor having a variable work functionMOTOROLA INC·Filed 1991·Granted May 11, 1993·69 cites·7 claims
- 2985US7387947B2Method for transferring a thin layer including a controlled disturbance of a crystalline structureSOITEC SILICON ON INSULATOR·Filed 2005·Granted Jun 17, 2008·14 cites·20 claims
- 3085US7232743B2Semiconductor structure for providing strained crystalline layer on insulator and method for fabricating sameSOITEC SILICON ON INSULATOR·Filed 2005·Granted Jun 19, 2007·9 cites·25 claims
- 3185US6207494B1Isolation collar nitride liner for DRAM process improvementINFINEON TECHNOLOGIES CORP·Filed 1999·Granted Mar 27, 2001·77 cites·34 claims
- 3285US5538922AMethod for forming contact to a semiconductor deviceMOTOROLA INC·Filed 1995·Granted Jul 23, 1996·74 cites·62 claims
- 3384US7407869B2Method for manufacturing a free-standing substrate made of monocrystalline semiconductor materialSOITEC SILICON ON INSULATOR·Filed 2005·Granted Aug 5, 2008·12 cites·22 claims
- 3484US5061647AITLDD transistor having variable work function and method for fabricating the sameMOTOROLA INC·Filed 1990·Granted Oct 29, 1991·61 cites·16 claims
- 3583US7022586B2Method for recycling a substrateSOITEC SILICON ON INSULATOR·Filed 2003·Granted Apr 4, 2006·34 cites·29 claims
- 3682US8664712B2Flash memory cell on SeOI having a second control gate buried under the insulating layerMAZURE CARLOS·Filed 2010·Granted Mar 4, 2014·6 cites·17 claims
- 3782US8241942B2Method of fabricating a back-illuminated image sensorBOURDELLE KONSTANTIN·Filed 2009·Granted Aug 14, 2012·6 cites·19 claims
- 3882US5256588AMethod for forming a transistor and a capacitor for use in a vertically stacked dynamic random access memory cellMOTOROLA INC·Filed 1992·Granted Oct 26, 1993·41 cites·18 claims
- 3981US9159400B2Semiconductor memory having staggered sense amplifiers associated with a local column decoderFERRANT RICHARD·Filed 2012·Granted Oct 13, 2015·8 cites·20 claims
- 4081US8735946B2Substrate having a charged zone in an insulating buried layerSOITEC SILICON ON INSULATOR·Filed 2013·Granted May 27, 2014·4 cites·16 claims
- 4181US8035163B2Low-cost double-structure substrates and methods for their manufactureSOITEC SILICON ON INSULATOR·Filed 2009·Granted Oct 11, 2011·5 cites·17 claims
- 4280US8358552B2Nano-sense amplifierSOITEC SILICON ON INSULATOR·Filed 2010·Granted Jan 22, 2013·6 cites·22 claims
- 4379US9490264B2Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said deviceMAZURE CARLOS·Filed 2011·Granted Nov 8, 2016·5 cites·14 claims
- 4479US8223582B2Pseudo-inverter circuit on SeOIMAZURE CARLOS·Filed 2010·Granted Jul 17, 2012·6 cites·21 claims
- 4579US5252849ATransistor useful for further vertical integration and method of formationMOTOROLA INC·Filed 1992·Granted Oct 12, 1993·40 cites·10 claims
- 4678US9035474B2Method for manufacturing a semiconductor substrateMAZURE CARLOS·Filed 2010·Granted May 19, 2015·4 cites·15 claims
- 4778US8455938B2Device comprising a field-effect transistor in a silicon-on-insulatorNGUYEN BICH-YEN·Filed 2010·Granted Jun 4, 2013·5 cites·20 claims
- 4878US5962069AProcess for fabricating layered superlattice materials and AB03 type metal oxides without exposure to oxygen at high temperaturesSYMETRIX CORP·Filed 1997·Granted Oct 5, 1999·52 cites·26 claims
- 4977US5213989AMethod for forming a grown bipolar electrode contact using a sidewall seedMOTOROLA INC·Filed 1992·Granted May 25, 1993·57 cites·20 claims
- 5076US8535996B2Substrate having a charged zone in an insulating buried layerSHAHEEN MOHAMAD·Filed 2008·Granted Sep 17, 2013·6 cites·11 claims
Showing the top 50 of 90 patent records by PatentIndex Score.
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