Inventor · disambiguated record
Cedric Denis Robert Airaud
Also filed as: AIRAUD CEDRIC · AIRAUD CEDRIC DENIS ROBERT · AIRAUD CÉDRIC DENIS ROBERT
43 granted patents·3 pending applications·146 citations·filing 2003–2023
96Inventor score
Top patents by PatentIndex Score
46 records- 0193US10198267B2Register renaming using snapshot buffersADVANCED RISC MACH LTD·Filed 2016·Granted Feb 5, 2019·23 cites·10 claims
- 0290US9424045B2Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unitADVANCED RISC MACH LTD·Filed 2013·Granted Aug 23, 2016·17 cites·21 claims
- 0385US7925868B2Suppressing register renaming for conditional instructions predicted as not executedADVANCED RISC MACH LTD·Filed 2007·Granted Apr 12, 2011·18 cites·16 claims
- 0484US12236241B2Data processing apparatus with selectively delayed transmission of operandsADVANCED RISC MACH LTD·Filed 2023·Granted Feb 25, 2025·1 cites·18 claims
- 0584US12141069B2Prefetch store filteringADVANCED RISC MACH LTD·Filed 2022·Granted Nov 12, 2024·1 cites·13 claims
- 0683US7624253B2Determining register availability for register renamingADVANCED RISC MACH LTD·Filed 2006·Granted Nov 24, 2009·15 cites·23 claims
- 0782US11907722B2Methods and apparatus for storing prefetch metadataADVANCED RISC MACH LTD·Filed 2022·Granted Feb 20, 2024·2 cites·19 claims
- 0881US9286069B2Dynamic write port re-arbitrationADVANCED RISC MACH LTD·Filed 2012·Granted Mar 15, 2016·7 cites·19 claims
- 0978US12045618B2Data processing apparatus and method for generating prefetches based on a nested prefetch patternADVANCED RISC MACH LTD·Filed 2021·Granted Jul 23, 2024·1 cites·20 claims
- 1078US7152186B2Cross-triggering of processing devicesADVANCED RISC MACH LTD·Filed 2003·Granted Dec 19, 2006·30 cites·44 claims
- 1177US7856532B2Cache logic, data processing apparatus including cache logic, and a method of operating cache logicADVANCED RISC MACH LTD·Filed 2006·Granted Dec 21, 2010·9 cites·12 claims
- 1274US9311087B2Sticky bit update within a speculative execution processing environmentADVANCED RISC MACH LTD·Filed 2012·Granted Apr 12, 2016·4 cites·18 claims
- 1373US10635445B2Handling modifications to permitted program counter ranges in a data processing apparatusADVANCED RISC MACH LTD·Filed 2018·Granted Apr 28, 2020·2 cites·15 claims
- 1466US7472225B2Caching dataADVANCED RISC MACH LTD·Filed 2005·Granted Dec 30, 2008·5 cites·23 claims
- 1565US7434007B2Management of cache memories in a data processing apparatusADVANCED RISC MACH LTD·Filed 2005·Granted Oct 7, 2008·5 cites·10 claims
- 1662US12112169B2Register freeing latencyADVANCED RISC MACH LTD·Filed 2023·Granted Oct 8, 2024·0 cites·16 claims
- 1761US9400655B2Technique for freeing renamed registersADVANCED RISC MACH LTD·Filed 2013·Granted Jul 26, 2016·1 cites·20 claims
- 1861US8352794B2Control of clock gatingADVANCED RISC MACH LTD·Filed 2009·Granted Jan 8, 2013·2 cites·21 claims
- 1960US9361111B2Tracking speculative execution of instructions for a register renaming data storeADVANCED RISC MACH LTD·Filed 2013·Granted Jun 7, 2016·1 cites·24 claims
- 2060US7698537B2Data processing apparatus for processing a stream of instructions in first and second processing blocks with the first processing block supporting register renaming and the second processing block not supporting register renamingADVANCED RISC MACH LTD·Filed 2006·Granted Apr 13, 2010·2 cites·18 claims
- 2159US12340216B1Control of instruction issue based on issue groupsADVANCED RISC MACH LTD·Filed 2023·Granted Jun 24, 2025·0 cites·20 claims
- 2255US12292834B2Cache prefetchingADVANCED RISC MACH LTD·Filed 2023·Granted May 6, 2025·0 cites·18 claims
- 2354US2025208874A1Apparatus, system, chip-containing product and non-transitory computer-readable mediumADVANCED RISC MACH LTD·Filed 2023·Application pending·0 cites
- 2453US11113028B2Apparatus and method for performing an index operationADVANCED RISC MACH LTD·Filed 2019·Granted Sep 7, 2021·0 cites·19 claims
- 2551US11580032B2Technique for training a prediction apparatusADVANCED RISC MACH LTD·Filed 2021·Granted Feb 14, 2023·0 cites·16 claims
- 2650US12360767B2Data processing apparatus, method and virtual machineADVANCED RISC MACH LTD·Filed 2023·Granted Jul 15, 2025·0 cites·16 claims
- 2747US11157277B2Data processing apparatus with respective banked registers for exception levelsADVANCED RISC MACH LTD·Filed 2019·Granted Oct 26, 2021·0 cites·9 claims
- 2847US11132202B2Cache control circuitry and methodsADVANCED RISC MACH LTD·Filed 2019·Granted Sep 28, 2021·0 cites·12 claims
- 2947US10310735B2Data storageADVANCED RISC MACH LTD·Filed 2017·Granted Jun 4, 2019·0 cites·13 claims
- 3046US12099846B2Shared unit instruction executionADVANCED RISC MACH LTD·Filed 2021·Granted Sep 24, 2024·0 cites·11 claims
- 3146US11010159B2Bit processing involving bit-level permutation instructions or operationsADVANCED RISC MACH LTD·Filed 2018·Granted May 18, 2021·0 cites·13 claims
- 3246US10846098B2Execution pipeline adaptationADVANCED RISC MACH LTD·Filed 2018·Granted Nov 24, 2020·0 cites·17 claims
- 3346US9170819B2Forwarding condition information from first processing circuitry to second processing circuitryADVANCED RISC MACH LTD·Filed 2013·Granted Oct 27, 2015·0 cites·20 claims
- 3446US7844800B2Method for renaming a large number of registers in a data processing system using a background channelADVANCED RISC MACH LTD·Filed 2007·Granted Nov 30, 2010·0 cites·24 claims
- 3545US11537522B2Determining a tag value for use in a tag-guarded memoryADVANCED RISC MACH LTD·Filed 2019·Granted Dec 27, 2022·0 cites·18 claims
- 3645US11036511B2Processing of a temporary-register-using instruction including determining whether to process a register move micro-operation for transferring data from a first register file to a second register file based on whether a temporary variable is still available in the second register fileADVANCED RISC MACH LTD·Filed 2019·Granted Jun 15, 2021·0 cites·19 claims
- 3745US7984269B2Data processing apparatus and method for reducing issue circuitry responsibility by using a predetermined pipeline stage to schedule a next operation in a sequence of operations defined by a complex instructionADVANCED RISC MACH LTD·Filed 2007·Granted Jul 19, 2011·0 cites·16 claims
- 3844US10725964B2Dynamic SIMD instruction issue target selectionADVANCED RISC MACH LTD·Filed 2018·Granted Jul 28, 2020·0 cites·16 claims
- 3944US10558462B2Apparatus and method for storing source operands for operationsADVANCED RISC MACH LTD·Filed 2018·Granted Feb 11, 2020·0 cites·18 claims
- 4043US2008077782A1Restoring a register renaming table within a processor following an exceptionADVANCED RISC MACH LTD·Filed 2006·Application pending·0 cites
- 4140US10545764B2Available register control for register renamingADVANCED RISC MACH LTD·Filed 2016·Granted Jan 28, 2020·0 cites·18 claims
- 4239US11531547B2Data processingADVANCED RISC MACH LTD·Filed 2021·Granted Dec 20, 2022·0 cites·13 claims
- 4339US10042640B2Processing queue managementADVANCED RISC MACH LTD·Filed 2016·Granted Aug 7, 2018·0 cites·10 claims
- 4435US9201656B2Data processing apparatus and method for performing register renaming for certain data processing operations without additional registersBRELOT JEAN-BAPTISTE·Filed 2011·Granted Dec 1, 2015·0 cites·11 claims
- 4533US9280675B2Encrypting and storing confidential dataBRELOT JEAN-BAPTISTE·Filed 2012·Granted Mar 8, 2016·0 cites·11 claims
- 4632US2012204056A1Power Signature ObfuscationAIRAUD CEDRIC DENIS ROBERT·Filed 2011·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →