Restoring a register renaming table within a processor following an exception

Abstract

Control logic for storing values relating to unresolved exception instructions within a buffer to enable a register renaming table within a processor to be restored following an exception is disclosed. The processor is operable to process a stream of instructions from an instruction set, the instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way. The processor comprises a physical set of registers operable to store data values being processed by the processor; and register renaming logic operable to receive a stream of decoded instructions and to map for each decoded instruction within the stream of decoded instructions, registers from an architectural set of registers associated with the instruction set to registers within the physical set of registers in dependence upon renaming values stored in the register renaming table; the control logic comprising a buffer and being operable: to identify exception and non-exception instructions within the decoded instruction stream and to group any non-exception instructions with a closest preceding exception instruction; to store in the buffer, register renaming values relating to any registers whose data values are modified by the group of instructions and which are renamed by the register renaming logic as a bundle of register renaming values associated with the exception instruction.

1 . Control logic for storing values relating to unresolved exception instructions within a buffer to enable a register renaming table within a processor to be restored following an exception;
 said processor being operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said processor comprising a physical set of registers operable to store data values being processed by said processor; and register renaming logic operable to receive a stream of decoded instructions and to map for each decoded instruction within said stream of decoded instructions, registers from an architectural set of registers associated with said instruction set to registers within said physical set of registers in dependence upon renaming values stored in said register renaming table;   said control logic comprising a buffer and being operable:   to identify exception and non-exception instructions within said decoded instruction stream and to group any non-exception instructions with a closest preceding exception instruction;   to store in said buffer, register renaming values relating to any registers whose data values are modified by said group of instructions and which are renamed by said register renaming logic as a bundle of register renaming values associated with said exception instruction.   
   
   
       2 . Control logic according to  claim 1 , said control logic being further operable to receive information relating to said exception instructions and indicative of whether said exception instructions are resolved such that they are assured to execute and not generate an exception; and
 in response to receiving information that an exception instruction is resolved to update a restore table within said processor with said register renaming values associated with said resolved exception instruction stored in said buffer; and   to flush said data associated with said resolved exception instruction from said buffer;   said restore table comprising renaming values for mapping registers from said architectural set to said physical set for a previously resolved exception instruction.   
   
   
       3 . Control logic according to  claim 1 , wherein said buffer comprises a FIFO buffer. 
   
   
       4 . Control logic according to  claim 1 , wherein said exception instructions comprise at least one of the following: memory access instructions and branch instructions. 
   
   
       5 . Control logic according to  claim 2 , said control logic further comprising a counter, operable to count a number of exception instructions identified, said counter value being stored as instruction identifier data within said buffer along with said register renaming values associated with said identified exception instruction, said control logic being operable to amend said counter value and said instruction identifier data in response to receipt of information that an exception instruction is resolved, such that said counter value indicates a number of unresolved exception instructions identified. 
   
   
       6 . Control logic according to  claim 5 , said control logic being operable to identify a group of instructions where no registers have data values that are modified by said group of instructions and no registers associated with said group of instructions are renamed by said register renaming logic, and to count said exception instruction from said group of instructions with said counter and not to store any data relating to said identified exception instruction in said buffer, said control logic being operable to amend said counter value in response to information that said identified exception instruction has been resolved. 
   
   
       7 . Control logic according to  claim 5 , said control logic being operable in response to said instruction identifier data indicating no unresolved exception instructions before said exception instruction in said instruction stream to update said restore table with said register renaming values associated with said instruction identifier data and then to flush said associated register renaming values and said instruction identifier data from said buffer. 
   
   
       8 . Control logic according to  claim 5 , said control logic being operable to store said register renaming values in a row in said buffer along with said instruction identifier data, and if said register renaming values will not fit in said row to store said remaining values in subsequent rows along with said instruction identifier data. 
   
   
       9 . Control logic according to  claim 2 , wherein said control logic is operable when updating said restore table to retrieve any renaming values that are to be overwritten and to output data from said retrieved renaming values relating to the physical register renamed. 
   
   
       10 . Control logic according to  claim 4 , said control logic being operable to identify said exception instructions as branch exception instructions and memory access exception instructions, said control logic comprising two counters, a branch counter operable to count a number of identified branch exception instruction, and a load counter operable to a number of identified memory access exception instructions, said values of said two counters being stored as instruction identifier data within said buffer along with said register renaming values relating to said identified exception instruction, said control logic being operable to amend said corresponding counter and said corresponding portion of said instruction identifier data in response to receipt of information that a branch or memory access exception instruction is resolved, such that said respective counter values indicate a number of unresolved exception instructions or a particular type identified. 
   
   
       11 . Control logic according to  claim 2 , said control logic being operable in response to receiving information that an exception instruction has generated an exception, to flush said buffer and to forward said restore table to said processor for overwriting said register renaming table. 
   
   
       12 . A data processing apparatus operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said processor comprising:
 control logic according to  claim 1 ;   an instruction decoder operable to receive and decode said stream of instructions;   a physical set of registers operable to store data values being processed by said data processing apparatus;   a data store operable to store a register renaming table comprising values that map each register of said architectural set to a register in said physical set for a decoded instruction;   register renaming logic operable to receive said stream of decoded instructions, and to populate said register renaming table with values appropriate for said received decoded instructions, said register renaming logic being operable to remap any registers associated with said received decoded instructions in dependence upon said values within said renaming table;   a further data store operable to store a recover table, said recover table comprising values from said remapping table for a previous instruction in said sequence of received decoded instructions, said previous instruction being a resolved exception instruction, a resolved exception instruction being an instruction that could have generated an exception but has been resolved not to.   
   
   
       13 . A data processing apparatus according to  claim 12 , said data processing apparatus comprising at least one exception instruction handling unit operable to determine whether an exception instruction will generate an exception or whether it is resolved not to and operable to provide said information to said control logic 
   
   
       14 . A data processing apparatus according to  claim 13 , said data processing apparatus comprising two exception instruction handling units one operable to handle decoded branch exception instructions and one operable to handle decoded memory access exception instructions, wherein said control logic is operable to identify said exception instructions as branch exception instructions and memory access exception instructions, said control logic comprising two counters, a branch counter operable to count a number of identified branch exception instruction, and a load counter operable to a number of identified memory access exception instructions, said values of said two counters being stored as instruction identifier data within said buffer along with said register renaming values relating to said identified exception instruction, said control logic being operable to amend said corresponding counter and said corresponding portion of said instruction identifier data in response to receipt of information from a corresponding exception instruction handling unit that a branch or memory access exception instruction is resolved, such that said respective counter values indicate a number of unresolved exception instructions or a particular type identified. 
   
   
       15 . A data processing apparatus according to  claim 13 , said data processing apparatus comprising control logic, said control logic being operable in response to said instruction handling unit indicating said exception instruction will generate an exception to overwrite said register renaming table with said restore table and to flush said buffer, said data processing apparatus being operable to force said program counter. 
   
   
       16 . A data processing apparatus according to  claim 15 , wherein said control logic is operable when updating said restore table to retrieve any renaming values that are to be overwritten and to output data relating to a physical register that has been overwritten to said register renaming logic, said register renaming logic being operable to determine a free list of physical registers available to be allocated from said received data. 
   
   
       17 . A method for storing values relating to unresolved exception instructions within a buffer to enable a register renaming table within a processor to be restored following an exception, the processor being operable to process a stream of instructions from an instruction set, the instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, the processor comprising a physical set of registers operable to store data values being processed by the processor; and register renaming logic operable to map for each decoded instruction, registers from an architectural set of registers associated with the instruction set to registers within said physical set of registers in dependence upon renaming values stored in said register renaming table; said method comprising the following steps:
 identifying exception and non-exception instructions within a decoded instruction stream;   grouping any non-exception instructions with a closest preceding exception instruction; and   storing in a buffer, register renaming values relating to any registers whose data values are modified by said group of instructions and which are renamed by said register renaming logic as a bundle of register renaming values associated with said exception instruction.   
   
   
       18 . Control means for storing values relating to unresolved exception instructions within a buffer storage means to enable a register renaming table within a processor to be restored following an exception;
 said processor being operable to process a stream of instructions from an instruction set, said instruction set comprising exception instructions and non-exception instructions, exception instructions being instructions that may generate an exception and non-exception instructions being instructions that execute in a statically determinable way, said processor comprising a physical set of registers operable to store data values being processed by said processor; and register renaming logic operable to map for each decoded instruction, registers from an architectural set of registers associated with said instruction set to registers within said physical set of registers in dependence upon renaming values stored in said register renaming table;   said control means comprising a buffer storage means and being operable:   to identify exception and non-exception instructions within a decoded instruction stream and to group any non-exception instructions with a closest preceding exception instruction;   to store in said buffer storage means, register renaming values relating to any registers whose data values are modified by said group of instructions and which are renamed by said register renaming logic as a bundle of register renaming values associated with said exception instruction.