Inventor · disambiguated record
Chang-Yun Chang
Also filed as: CHANG CHANG-YUN
84 granted patents·11 pending applications·1,388 citations·filing 2004–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD50TAIWAN SEMICONDUCTOR MFG20SHIEH MING-FENG5YUAN FENG4CHEN HAO-YU3
Top patents by PatentIndex Score
95 records- 0199US8039179B2Integrated circuit layout designTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Oct 18, 2011·121 cites·20 claims
- 0298US8610240B2Integrated circuit with multi recessed shallow trench isolationLEE TSUNG-LIN·Filed 2010·Granted Dec 17, 2013·192 cites·15 claims
- 0398US8110466B2Cross OD FinFET patterningSHIEH MING-FENG·Filed 2010·Granted Feb 7, 2012·44 cites·14 claims
- 0498US7862962B2Integrated circuit layout designTAIWAN SEMICONDUCTOR MFG·Filed 2009·Granted Jan 4, 2011·46 cites·20 claims
- 0598US7425740B2Method and structure for a 1T-RAM bit cell and macroTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Sep 16, 2008·278 cites·26 claims
- 0697US10319581B1Cut metal gate process for reducing transistor spacingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jun 11, 2019·14 cites·20 claims
- 0797US8941153B2FinFETs with different fin heightsLEE TSUNG-LIN·Filed 2010·Granted Jan 27, 2015·46 cites·18 claims
- 0897US8373238B2FinFETs with multiple Fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Feb 12, 2013·39 cites·17 claims
- 0996US8847361B2Memory cell layoutTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 30, 2014·18 cites·20 claims
- 1096US8735991B2High gate density devices and methodsSHIEH MING-FENG·Filed 2011·Granted May 27, 2014·24 cites·20 claims
- 1196US8174073B2Integrated circuit structures with multiple FinFETsLEE TSUNG-LIN·Filed 2007·Granted May 8, 2012·51 cites·3 claims
- 1295US11508623B2Local gate height tuning by CMP and dummy gate designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 22, 2022·3 cites·20 claims
- 1395US9324866B2Structure and method for transistor with line end extensionYU SHAO-MING·Filed 2012·Granted Apr 26, 2016·30 cites·15 claims
- 1495US8748993B2FinFETs with multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Jun 10, 2014·18 cites·20 claims
- 1595US8673709B2FinFETs with multiple fin heightsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Mar 18, 2014·17 cites·20 claims
- 1695US8519481B2Voids in STI regions for forming bulk FinFETsYUAN FENG·Filed 2009·Granted Aug 27, 2013·35 cites·29 claims
- 1795US7381649B2Structure for a multiple-gate FET device and a method for its fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jun 3, 2008·30 cites·19 claims
- 1895US7300837B2FinFET transistor device on SOI and method of fabricationTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Nov 27, 2007·161 cites·29 claims
- 1994US11817354B2Local gate height tuning by cmp and dummy gate designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Nov 14, 2023·2 cites·20 claims
- 2094US9953885B2STI shape near fin bottom of Si fin in bulk FinFETYUAN FENG·Filed 2010·Granted Apr 24, 2018·24 cites·20 claims
- 2193US8847295B2Structure and method for fabricating fin devicesTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 30, 2014·13 cites·20 claims
- 2293US8241823B2Method of fabrication of a semiconductor device having reduced pitchSHIEH MING-FENG·Filed 2011·Granted Aug 14, 2012·11 cites·20 claims
- 2392US10930564B2Metal gate structure cutting processTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 23, 2021·7 cites·20 claims
- 2492US8723271B2Voids in STI regions for forming bulk FinFETsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted May 13, 2014·12 cites·20 claims
- 2591US10510894B2Isolation structure having different distances to adjacent FinFET devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 17, 2019·5 cites·20 claims
- 2690US2025308882A1Cut metal gate process for reducing transistor spacingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2789US8865539B2Fully depleted SOI multiple threshold voltage applicationCHEN HAO-YU·Filed 2011·Granted Oct 21, 2014·12 cites·20 claims
- 2889US2025357128A1Methods of forming semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2988US11315933B2SRAM structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Apr 26, 2022·4 cites·20 claims
- 3088US9362290B2Memory cell layoutLIAW JHON-JHY·Filed 2010·Granted Jun 7, 2016·9 cites·19 claims
- 3188US8871597B2High gate density devices and methodsTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Oct 28, 2014·7 cites·20 claims
- 3288US8846465B2Integrated circuit with multi recessed shallow trench isolationTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 30, 2014·8 cites·20 claims
- 3387US8592918B2Forming inter-device STI regions and intra-device STI regions using different dielectric materialsYUAN FENG·Filed 2010·Granted Nov 26, 2013·8 cites·20 claims
- 3487US7382023B2Fully depleted SOI multiple threshold voltage applicationTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jun 3, 2008·13 cites·31 claims
- 3586US12374542B2Cut metal gate process for reducing transistor spacingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 29, 2025·0 cites·20 claims
- 3686US9711412B2FinFETs with different fin heightsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jul 18, 2017·3 cites·20 claims
- 3785US8813014B2Semiconductor device and method for making the same using semiconductor fin density design rulesYU SHAO-MING·Filed 2009·Granted Aug 19, 2014·12 cites·19 claims
- 3883US12243782B2Local gate height tuning by CMP and dummy gate designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Mar 4, 2025·0 cites·20 claims
- 3983US12218239B2Structure and method for providing line end extensions for fin-type active regionsMOSAID TECH INCORPORATED·Filed 2023·Granted Feb 4, 2025·0 cites·16 claims
- 4083US12009266B2Structure for fringing capacitance controlTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Jun 11, 2024·2 cites·20 claims
- 4183US8846466B2Forming inter-device STI regions and intra-device STI regions using different dielectric materialsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 30, 2014·5 cites·20 claims
- 4282US11398384B2Methods for manufacturing a transistor gate by non-directional implantation of impurities in a gate spacerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jul 26, 2022·1 cites·20 claims
- 4382US9917192B2Structure and method for transistors with line end extensionTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Mar 13, 2018·3 cites·19 claims
- 4482US8796156B2Cross OD FinFET patterningSHIEH MING-FENG·Filed 2012·Granted Aug 5, 2014·5 cites·13 claims
- 4582US7511988B2Static noise-immune SRAM cellsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Mar 31, 2009·15 cites·16 claims
- 4682US2024379364A1Semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 4781US11574846B2Gate formation of semiconductor devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Feb 7, 2023·1 cites·20 claims
- 4881US9673328B2Structure and method for providing line end extensions for fin-type active regionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jun 6, 2017·4 cites·17 claims
- 4980US11721544B2Cut metal gate process for reducing transistor spacingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 8, 2023·0 cites·20 claims
- 5080US11239365B2Structure and method for providing line end extensions for fin-type active regionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Feb 1, 2022·1 cites·20 claims
Showing the top 50 of 95 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →