Inventor · disambiguated record
Chandrashekar L. Chetput
Also filed as: CHETPUT CHANDRASHEKAR L · CHETPUT CHANDRASHEKAR LAKSHMINARAYANAN
20 granted patents·166 citations·filing 2004–2020
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0193US10769336B1System, method, and computer program product for connecting power supplies in a mixed signal designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Sep 8, 2020·10 cites·20 claims
- 0291US8296699B1Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verificationCHETPUT CHANDRASHEKAR L·Filed 2010·Granted Oct 23, 2012·21 cites·36 claims
- 0388US8201137B1Method and apparatus for AMS simulation of integrated circuit designBHUSHAN PRANAV·Filed 2009·Granted Jun 12, 2012·24 cites·10 claims
- 0485US8234617B2Method and system for re-using digital assertions in a mixed signal designCHETPUT CHANDRASHEKAR L·Filed 2009·Granted Jul 31, 2012·16 cites·30 claims
- 0584US8732630B1Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description languageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted May 20, 2014·9 cites·32 claims
- 0684US7797659B2Analog/digital partitioning of circuit designs for simulationCADENCE DESIGN SYSTEMS INC·Filed 2007·Granted Sep 14, 2010·13 cites·11 claims
- 0783US8661402B2Method and apparatus for AMS simulation of integrated circuit designBHUSHAN PRANAV·Filed 2012·Granted Feb 25, 2014·8 cites·10 claims
- 0881US9501592B1Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description languageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Nov 22, 2016·7 cites·29 claims
- 0980US8255191B1Using real value models in simulation of analog and mixed-signal systemsKOLPEKWAR ABHIJEET·Filed 2009·Granted Aug 28, 2012·12 cites·28 claims
- 1079US10380294B1System, method, and computer program product for generating bidirectional real number models in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2017·Granted Aug 13, 2019·3 cites·18 claims
- 1179US8949753B1Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description languageCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 3, 2015·6 cites·31 claims
- 1275US8448116B2Analog/digital partitioning of circuit designs for simulationCHETPUT CHANDRASHEKAR L·Filed 2010·Granted May 21, 2013·4 cites·5 claims
- 1375US7260792B2Modeling a mixed-language mixed-signal designCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Aug 21, 2007·9 cites·13 claims
- 1472US8578322B2Method and apparatus for AMS simulation of integrated circuit designBHUSHAN PRANAV·Filed 2012·Granted Nov 5, 2013·3 cites·6 claims
- 1570US7979262B1Method for verifying connectivity of electrical circuit componentsCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Jul 12, 2011·6 cites·50 claims
- 1668US9886538B1System and method for using heterogeneous hierarchical configurations for electronic design reuseCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Feb 6, 2018·2 cites·17 claims
- 1764US8504346B1Method and mechanism for performing mixed-signal simulation of electronic designs having complex digital signal types or modelsKOLPEKWAR ABHIJEET·Filed 2009·Granted Aug 6, 2013·3 cites·38 claims
- 1862US7251795B2Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal designCADENCE DESIGN SYSTEMS INC·Filed 2004·Granted Jul 31, 2007·10 cites·18 claims
- 1953US8640073B2Analog/digital partitioning of circuit designs for simulationCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Jan 28, 2014·0 cites·6 claims
- 2052US11334704B1System, method, and computer program product for mixed signal verificationCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted May 17, 2022·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →