Inventor · disambiguated record
Ching-Tsun Chou
Also filed as: CHOU CHING-TSUN
13 granted patents·7 pending applications·50 citations·filing 2001–2022
88Inventor score
Top patents by PatentIndex Score
20 records- 0182US8694736B2Satisfying memory ordering requirements between partial reads and non-snoop accessesBEERS ROBERT H·Filed 2012·Granted Apr 8, 2014·5 cites·20 claims
- 0281US7991875B2Link level retry schemeINTEL CORP·Filed 2006·Granted Aug 2, 2011·10 cites·21 claims
- 0377US7016304B2Link level retry schemeINTEL CORP·Filed 2001·Granted Mar 21, 2006·25 cites·17 claims
- 0475US8250311B2Satisfying memory ordering requirements between partial reads and non-snoop accessesBEERS ROBERT H·Filed 2008·Granted Aug 21, 2012·5 cites·15 claims
- 0566US10761849B2Processors, methods, systems, and instruction conversion modules for instructions with compact instruction encodings due to use of context of a prior instructionINTEL CORP·Filed 2016·Granted Sep 1, 2020·1 cites·25 claims
- 0660US10019366B2Satisfying memory ordering requirements between partial reads and non-snoop accessesINTEL CORP·Filed 2017·Granted Jul 10, 2018·0 cites·6 claims
- 0759US9703712B2Satisfying memory ordering requirements between partial reads and non-snoop accessesINTEL CORP·Filed 2014·Granted Jul 11, 2017·0 cites·16 claims
- 0857US9058271B2Satisfying memory ordering requirements between partial reads and non-snoop accessesINTEL CORP·Filed 2013·Granted Jun 16, 2015·0 cites·19 claims
- 0955US8693319B2Scheme for avoiding deadlock in multi-ring interconnect, with additional application to congestion controlCHOU CHING-TSUN·Filed 2008·Granted Apr 8, 2014·1 cites·31 claims
- 1055US8099558B2Fairness mechanism for starvation prevention in directory-based cache coherence protocolsPARK SEUNGJOON·Filed 2009·Granted Jan 17, 2012·2 cites·30 claims
- 1154US8443337B2Methodology and tools for tabled-based protocol specification and model generationCHOU CHING-TSUN·Filed 2008·Granted May 14, 2013·1 cites·15 claims
- 1250US2024220261A1Instructions and support for conditional load and storeAGRON JASON·Filed 2022·Application pending·0 cites
- 1350US2024220262A1Instructions and support for conditional comparison and testAGRON JASON·Filed 2022·Application pending·0 cites
- 1450US2024220257A1Instructions and support for stack push and popAGRON JASON·Filed 2022·Application pending·0 cites
- 1549US2024220260A1Prefix extensions for extended general purpose registers with optimization features for non-destructive destinations and flags suppressionAGRON JASON·Filed 2022·Application pending·0 cites
- 1648US10120686B2Eliminating redundant store instructions from execution while maintaining total store orderINTEL CORP·Filed 2016·Granted Nov 6, 2018·0 cites·20 claims
- 1748US8205045B2Satisfying memory ordering requirements between partial writes and non-snoop accessesBEERS ROBERT H·Filed 2008·Granted Jun 19, 2012·0 cites·20 claims
- 1847US2014112145A1Scheme for avoiding deadlock in multi-ring interconnect, with additional application to congestion controlCHOU CHING-TSUN·Filed 2013·Application pending·0 cites
- 1945US2009254712A1Adaptive cache organization for chip multiprocessorsCHERUKURI NAVEEN·Filed 2008·Application pending·0 cites
- 2041US2009171647A1Interconnect architectural state coverage measurement methodologyMANNAVA PHANINDRA·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →