Inventor · disambiguated record
Chung Chyung Han
Also filed as: HAN CHUNG CHYUNG · HAN CHUNG CHYUNG (JUSTIN) · HAN CHUNG CHYUNG JASON
14 granted patents·3 pending applications·227 citations·filing 1995–2016
93Inventor score
Top patents by PatentIndex Score
17 records- 0196US9768144B2Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrateMARVELL WORLD TRADE LTD·Filed 2016·Granted Sep 19, 2017·11 cites·19 claims
- 0288US5793088AStructure for controlling threshold voltage of MOSFETINTEGRATED DEVICE TECH·Filed 1996·Granted Aug 11, 1998·98 cites·21 claims
- 0374US9257410B2Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrateWU ALBERT·Filed 2011·Granted Feb 9, 2016·2 cites·26 claims
- 0469US8946890B2Power/ground layout for chipsSUTARDJA SEHAT·Filed 2011·Granted Feb 3, 2015·2 cites·15 claims
- 0566US5831313AStructure for improving latch-up immunity and interwell isolation in a semiconductor deviceINTEGRATED DEVICE TECH·Filed 1996·Granted Nov 3, 1998·35 cites·17 claims
- 0665US5654213AMethod for fabricating a CMOS deviceINTEGRATED DEVICE TECH·Filed 1995·Granted Aug 5, 1997·26 cites·39 claims
- 0757US8921938B1Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wellsMARVELL INT LTD·Filed 2013·Granted Dec 30, 2014·1 cites·16 claims
- 0857US2014124961A1Techniques and configurations for recessed semiconductor substratesMARVELL WORLD TRADE LTD·Filed 2014·Application pending·0 cites
- 0955US9391045B2Recessed semiconductor substrates and associated techniquesMARVELL WORLD TRADE LTD·Filed 2015·Granted Jul 12, 2016·0 cites·20 claims
- 1052US9034730B2Recessed semiconductor substrates and associated techniquesWU ALBERT·Filed 2011·Granted May 19, 2015·0 cites·23 claims
- 1151US2011186960A1Techniques and configurations for recessed semiconductor substratesWU ALBERT·Filed 2011·Application pending·0 cites
- 1250US6063676AMosfet with raised source and drain regionsINTEGRATED DEVICE TECH·Filed 1997·Granted May 16, 2000·17 cites·9 claims
- 1348US6127710ACMOS structure having a gate without spacersINTEGRATED DEVICE TECH·Filed 1997·Granted Oct 3, 2000·11 cites·10 claims
- 1446US5750424AMethod for fabricating a CMOS deviceINTEGRATED DEVICE TECH·Filed 1996·Granted May 12, 1998·10 cites·17 claims
- 1544US2015155202A1Power/ground layout for chipsMARVELL WORLD TRADE LTD·Filed 2015·Application pending·0 cites
- 1643US6017785AMethod for improving latch-up immunity and interwell isolation in a semiconductor deviceINTEGRATED DEVICE TECH·Filed 1996·Granted Jan 25, 2000·8 cites·31 claims
- 1737US6043129AHigh density MOSFET with raised source and drain regionsINTEGRATED DEVICE TECH·Filed 1997·Granted Mar 28, 2000·6 cites·57 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →