Techniques and configurations for recessed semiconductor substrates

Abstract

Embodiments of the present disclosure provide a method comprising providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface, forming a dielectric film on the first surface of the semiconductor substrate, forming a redistribution layer on the dielectric film, electrically coupling one or more dies to the redistribution layer, forming a molding compound on the semiconductor substrate, recessing the second surface of the semiconductor substrate, forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies. Other embodiments may be described and/or claimed.

1 . A method comprising:
 providing a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface;   forming a dielectric film on the first surface of the semiconductor substrate;   forming a redistribution layer on the dielectric film;   electrically coupling one or more dies to the redistribution layer;   forming a molding compound on the semiconductor substrate;   recessing the second surface of the semiconductor substrate;   forming one or more channels through the recessed second surface of the semiconductor substrate to expose the redistribution layer; and   forming one or more package interconnect structures in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer, the one or more package interconnect structures to route electrical signals of the one or more dies.   
     
     
         2 . The method of  claim 1 , wherein the redistribution layer is formed by depositing an electrically conductive material on the dielectric film. 
     
     
         3 . The method of  claim 1 , wherein the one or more dies are coupled to the redistribution layer in a flip-chip configuration. 
     
     
         4 . The method of  claim 1 , wherein the molding compound is formed by depositing an electrically insulative material to substantially encapsulate the one or more dies. 
     
     
         5 . The method of  claim 1 , wherein the semiconductor substrate is recessed by a grinding process or an etch process. 
     
     
         6 . The method of  claim 1 , wherein the semiconductor substrate is recessed such that the semiconductor substrate has a thickness between about 50 microns and about 300 microns. 
     
     
         7 . The method of  claim 1 , wherein the one or more channels are formed by:
 selectively removing semiconductor material of the semiconductor substrate; and   selectively removing dielectric material of the dielectric film.   
     
     
         8 . The method of  claim 1 , further comprising:
 forming one or more under-ball metallization (UBM) structures in the one or more channels, the one or more UBM structures being formed on (i) the redistribution layer that is exposed by forming the one or more channels and (ii) the semiconductor substrate within the one or more channels, wherein the one or more package interconnect structures are coupled to the one or more UBM structures.   
     
     
         9 . The method of  claim 1 , wherein the one or more package interconnect structures comprise solder balls that are formed by at least one of (i) screen printing, (ii) electrical plating, and (iii) solder ball placement. 
     
     
         10 . The method of  claim 1 , further comprising:
 forming an underfill layer between (i) the one or more dies and (ii) the semiconductor substrate.   
     
     
         11 . The method of  claim 1 , wherein the one or more channels are formed subsequent to the molding compound being formed; and
 the molding compound is used as a mechanical carrier to support the semiconductor substrate when the second surface of the semiconductor substrate is being recessed.   
     
     
         12 . An apparatus comprising:
 a semiconductor substrate having (i) a first surface and (ii) a second surface that is disposed opposite to the first surface;   a dielectric film formed on the first surface of the semiconductor substrate;   a redistribution layer formed on the dielectric film;   one or more dies electrically coupled to the redistribution layer;   a molding compound formed on the semiconductor substrate;   one or more channels formed through the second surface of the semiconductor substrate; and   one or more package interconnect structures disposed in the one or more channels, the one or more package interconnect structures being electrically coupled to the redistribution layer through the one or more channels to route electrical signals of the one or more dies.   
     
     
         13 . The apparatus of  claim 12 , wherein the one or more dies are coupled to the redistribution layer in a flip-chip configuration using one or more bumps. 
     
     
         14 . The apparatus of  claim 12 , wherein the molding compound substantially encapsulates the one or more dies. 
     
     
         15 . The apparatus of  claim 12 , wherein the second surface of the semiconductor substrate is recessed such that the semiconductor substrate has a thickness between about 50 microns and about 300 microns. 
     
     
         16 . The apparatus of  claim 12 , further comprising:
 one or more under-ball metallization (UBM) structures formed in the one or more channels, the one or more UBM structures being formed on (i) the redistribution layer and (ii) the semiconductor substrate within the one or more channels, wherein the one or more package interconnect structures are coupled to the one or more UBM structures.   
     
     
         17 . The apparatus of  claim 12 , further comprising:
 an underfill layer formed between (i) the one or more dies and (ii) the semiconductor substrate.   
     
     
         18 . The apparatus of  claim 12 , wherein:
 the one or more package interconnect structures comprise solder balls to route electrical signals of the one or more dies; and   the redistribution layer comprises an electrically conductive material to route the electrical signals of the one or more dies.   
     
     
         19 . The apparatus of  claim 12 , wherein:
 the semiconductor substrate comprises silicon;   the one or more dies comprise silicon; and   the one or more channels comprise one or more through-silicon vias.   
     
     
         20 . The apparatus of  claim 19 , wherein:
 the molding compound and the semiconductor substrate have a coefficient of thermal expansion (CTE) that is the same or substantially similar; and   the one or more through-silicon vias are tapered.