Inventor · disambiguated record
Chuan-Cheng Cheng
Also filed as: CHENG CHUAN-CHENG
29 granted patents·5 pending applications·185 citations·filing 2001–2022
96Inventor score
Top patents by PatentIndex Score
34 records- 0196US9768144B2Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrateMARVELL WORLD TRADE LTD·Filed 2016·Granted Sep 19, 2017·11 cites·19 claims
- 0296US7808075B1Integrated circuit devices with ESD and I/O protectionMARVELL INT LTD·Filed 2006·Granted Oct 5, 2010·47 cites·51 claims
- 0395US7883947B1Method of fabricating a device with ESD and I/O protectionMARVELL INT LTD·Filed 2010·Granted Feb 8, 2011·15 cites·20 claims
- 0490US8044733B1Stress tolerant differential colpitts voltage controlled oscillatorsMARVELL INT LTD·Filed 2009·Granted Oct 25, 2011·19 cites·19 claims
- 0589US9275929B2Package assembly having a semiconductor substrateMARVELL WORLD TRADE LTD·Filed 2015·Granted Mar 1, 2016·6 cites·20 claims
- 0688US7704805B1Fuse structures, methods of making and using the same, and integrated circuits including the sameMARVELL INT LTD·Filed 2008·Granted Apr 27, 2010·12 cites·23 claims
- 0784US10217669B2Isolation components for transistors formed on fin features of semiconductor substratesMARVELL WORLD TRADE LTD·Filed 2016·Granted Feb 26, 2019·3 cites·18 claims
- 0883US7820493B1Methods of making and using fuse structures, and integrated circuits including the sameMARVELL INT LTD·Filed 2008·Granted Oct 26, 2010·8 cites·15 claims
- 0974US9257410B2Package assembly including a semiconductor substrate in which a first portion of a surface of the semiconductor substrate is recessed relative to a second portion of the surface of the semiconductor substrate to form a recessed region in the semiconductor substrateWU ALBERT·Filed 2011·Granted Feb 9, 2016·2 cites·26 claims
- 1073US8372729B1Integrated circuit devices with ESD protection in scribe line, and methods for fabricating sameMARVELL INT LTD·Filed 2011·Granted Feb 12, 2013·2 cites·19 claims
- 1172US8049249B1Integrated circuit devices with ESD protection in scribe line, and methods for fabricating sameMARVELL INT LTD·Filed 2006·Granted Nov 1, 2011·3 cites·12 claims
- 1272US6495426B1Method for simultaneous formation of integrated capacitor and fuseLSI LOGIC CORP·Filed 2001·Granted Dec 17, 2002·16 cites·16 claims
- 1371US7589363B1Fuse structures, methods of making and using the same, and integrated circuits including the sameMARVELL INT LTD·Filed 2007·Granted Sep 15, 2009·3 cites·20 claims
- 1469US8946890B2Power/ground layout for chipsSUTARDJA SEHAT·Filed 2011·Granted Feb 3, 2015·2 cites·15 claims
- 1569US8861214B1High resistivity substrate for integrated passive device (IPD) applicationsWU ALBERT·Filed 2007·Granted Oct 14, 2014·4 cites·4 claims
- 1666US7344924B1Fuse structures, methods of making and using the same, and integrated circuits including the sameMARVELL INT LTD·Filed 2005·Granted Mar 18, 2008·2 cites·15 claims
- 1764US6940107B1Fuse structures, methods of making and using the same, and integrated circuits including the sameMARVELL INT LTD·Filed 2003·Granted Sep 6, 2005·8 cites·36 claims
- 1864US6627968B2Integrated capacitor and fuseLSI LOGIC CORP·Filed 2002·Granted Sep 30, 2003·10 cites·3 claims
- 1960US10784167B2Isolation components for transistors formed on fin features of semiconductor substratesMARVELL WORLD TRADE LTD·Filed 2018·Granted Sep 22, 2020·0 cites·20 claims
- 2058US12401326B2Reducing parasitic capacitanceQUALCOMM INC·Filed 2022·Granted Aug 26, 2025·0 cites·23 claims
- 2157US8921938B1Laterally diffused metal oxide semiconductor (LDMOS) device with overlapping wellsMARVELL INT LTD·Filed 2013·Granted Dec 30, 2014·1 cites·16 claims
- 2257US6627469B2Methods for forming semiconductor lenses on substratesCALIFORNIA INST OF TECHN·Filed 2001·Granted Sep 30, 2003·6 cites·20 claims
- 2357US2014124961A1Techniques and configurations for recessed semiconductor substratesMARVELL WORLD TRADE LTD·Filed 2014·Application pending·0 cites
- 2455US9391045B2Recessed semiconductor substrates and associated techniquesMARVELL WORLD TRADE LTD·Filed 2015·Granted Jul 12, 2016·0 cites·20 claims
- 2554US8753960B1Integrated circuit devices with electrostatic discharge (ESD) protection in scribe line regionsMARVELL INT LTD·Filed 2013·Granted Jun 17, 2014·0 cites·20 claims
- 2652US10622491B2Well doping for metal oxide semiconductor (MOS) varactorQUALCOMM INC·Filed 2018·Granted Apr 14, 2020·0 cites·18 claims
- 2752US9034730B2Recessed semiconductor substrates and associated techniquesWU ALBERT·Filed 2011·Granted May 19, 2015·0 cites·23 claims
- 2852US2014103452A1Isolation components for transistors formed on fin features of semiconductor substratesMARVELL WORLD TRADE LTD·Filed 2013·Application pending·0 cites
- 2951US6815342B1Low resistance metal interconnect lines and a process for fabricating themLSI LOGIC CORP·Filed 2001·Granted Nov 9, 2004·5 cites·7 claims
- 3051US2011186960A1Techniques and configurations for recessed semiconductor substratesWU ALBERT·Filed 2011·Application pending·0 cites
- 3146US9397218B2Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devicesMARVELL WORLD TRADE LTD·Filed 2014·Granted Jul 19, 2016·0 cites·20 claims
- 3246US2011175218A1Package assembly having a semiconductor substrateLIOU SHIANN-MING·Filed 2010·Application pending·0 cites
- 3344US2015155202A1Power/ground layout for chipsMARVELL WORLD TRADE LTD·Filed 2015·Application pending·0 cites
- 3432US9275985B1RC networks that include an integrated high resistance resistor on top of a MOS capacitorCHENG CHUAN-CHENG·Filed 2012·Granted Mar 1, 2016·0 cites·5 claims
Join the waitlist — get patent alerts
Get an alert when Chuan-Cheng Cheng files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →