Inventor · disambiguated record
Chiu-Yu Ku
Also filed as: KU CHIU-YU
5 granted patents·1 citations·filing 2010–2021
62Inventor score
Top patents by PatentIndex Score
5 records- 0174US10691867B2Identifying root cause of layout versus schematic errorsSYNOPSYS INC·Filed 2018·Granted Jun 23, 2020·1 cites·21 claims
- 0264US10970456B1Identifying root cause of layout versus schematic errorsSYNOPSYS INC·Filed 2020·Granted Apr 6, 2021·0 cites·20 claims
- 0354US11341310B1Layout-versus-schematic (LVS) debugging and error diagnosis via type of graph matchingSYNOPSYS INC·Filed 2020·Granted May 24, 2022·0 cites·20 claims
- 0445US11734489B2Circuit layout verificationSYNOPSYS INC·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 0530US8826219B2Method and apparatus used for the physical validation of integrated circuitsKU CHIU-YU·Filed 2010·Granted Sep 2, 2014·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →