Inventor · disambiguated record
Chih-Chin Liao
Also filed as: LIAO CHIH-CHIN
53 granted patents·10 pending applications·411 citations·filing 1999–2021
98Inventor score
Files withSANDISK CORP14SILICONWARE PRECISION INDUSTRIES CO LTD12LIAO CHIH-CHIN9TAKIAR HEM6SANDISK TECHNOLOGIES INC5
Top patents by PatentIndex Score
63 records- 0196US9899347B1Wire bonded wide I/O semiconductor deviceSANDISK TECHNOLOGIES LLC·Filed 2017·Granted Feb 20, 2018·19 cites·26 claims
- 0295US7550834B2Stacked, interconnected semiconductor packagesSANDISK CORP·Filed 2006·Granted Jun 23, 2009·38 cites·15 claims
- 0394US10249587B1Semiconductor device including optional pad interconnectWESTERN DIGITAL TECH INC·Filed 2017·Granted Apr 2, 2019·11 cites·29 claims
- 0494US6570249B1Semiconductor packageSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2002·Granted May 27, 2003·84 cites·8 claims
- 0592US8415808B2Semiconductor device with die stack arrangement including staggered die and efficient wire bondingLIAO CHIH-CHIN·Filed 2010·Granted Apr 9, 2013·24 cites·8 claims
- 0692US7375415B2Die package with asymmetric leadframe connectionSANDISK CORP·Filed 2005·Granted May 20, 2008·23 cites·30 claims
- 0790US11234327B1Printed circuit board trace for galvanic effect reductionWESTERN DIGITAL TECH INC·Filed 2021·Granted Jan 25, 2022·4 cites·20 claims
- 0887US7538438B2Substrate warpage control and continuous electrical enhancementSANDISK CORP·Filed 2005·Granted May 26, 2009·15 cites·36 claims
- 0985US7746661B2Printed circuit board with coextensive electrical connectors and contact pad areasSANDISK CORP·Filed 2006·Granted Jun 29, 2010·8 cites·18 claims
- 1085US7355283B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK CORP·Filed 2005·Granted Apr 8, 2008·10 cites·12 claims
- 1184US11569155B2Substrate bonding pad having a multi-surface trace interfaceWESTERN DIGITAL TECH INC·Filed 2021·Granted Jan 31, 2023·1 cites·18 claims
- 1282US7615409B2Method of stacking and interconnecting semiconductor packages via electrical connectors extending between adjoining semiconductor packagesSANDISK CORP·Filed 2006·Granted Nov 10, 2009·8 cites·10 claims
- 1379US8878368B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK TECHNOLOGIES INC·Filed 2013·Granted Nov 4, 2014·3 cites·16 claims
- 1477US6593658B2Chip package capable of reducing moisture penetrationSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2001·Granted Jul 15, 2003·25 cites·7 claims
- 1576US8097495B2Die package with asymmetric leadframe connectionLEE MING HSUN·Filed 2008·Granted Jan 17, 2012·7 cites·15 claims
- 1675US10607955B2Heterogeneous fan-out structures for memory devicesSANDISK SEMICONDUCTOR SHANGHAI CO LTD·Filed 2017·Granted Mar 31, 2020·4 cites·10 claims
- 1774US9230919B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingSANDISK TECHNOLOGIES INC·Filed 2014·Granted Jan 5, 2016·2 cites·22 claims
- 1874US6399417B1Method of fabricating plated circuit lines over ball grid array substrateSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2001·Granted Jun 4, 2002·24 cites·7 claims
- 1972US8487441B2Rigid wave pattern design on chip carrier substrate and printed circuit board for semiconductor and electronic sub-system packagingCHIU CHIN-TIEN·Filed 2007·Granted Jul 16, 2013·4 cites·11 claims
- 2072US7806731B2Rounded contact fingers on substrate/PCB for crack preventionSANDISK CORP·Filed 2005·Granted Oct 5, 2010·5 cites·38 claims
- 2171US8470640B2Method of fabricating stacked semiconductor package with localized cavities for wire bondingTAKIAR HEM·Filed 2008·Granted Jun 25, 2013·5 cites·15 claims
- 2271US8053880B2Stacked, interconnected semiconductor packageSANDISK TECHNOLOGIES INC·Filed 2009·Granted Nov 8, 2011·4 cites·16 claims
- 2370US10249592B2Wire bonded wide I/O semiconductor deviceSANDISK TECHNOLOGIES LLC·Filed 2018·Granted Apr 2, 2019·1 cites·24 claims
- 2469US8129272B2Hidden plating tracesTAKIAR HEM·Filed 2009·Granted Mar 6, 2012·3 cites·16 claims
- 2569US7611927B2Method of minimizing kerf width on a semiconductor substrate panelSANDISK CORP·Filed 2007·Granted Nov 3, 2009·4 cites·27 claims
- 2668US7967184B2Padless substrate for surface mounted componentsSANDISK CORP·Filed 2005·Granted Jun 28, 2011·4 cites·6 claims
- 2767US8637963B2Radiation-shielded semiconductor deviceUPADHYAYULA SURESH KUMAR·Filed 2011·Granted Jan 28, 2014·3 cites·12 claims
- 2867US6689636B2Semiconductor device and fabrication method of the sameSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2003·Granted Feb 10, 2004·12 cites·8 claims
- 2966US8502375B2Corrugated die edge for stacked die semiconductor packageLIAO CHIH-CHIN·Filed 2010·Granted Aug 6, 2013·2 cites·34 claims
- 3063US11177239B2Semiconductor device including control switches to reduce pin capacitanceSANDISK INFORMATION TECH SHANGHAI CO LTD·Filed 2018·Granted Nov 16, 2021·1 cites·19 claims
- 3163US7663216B2High density three dimensional semiconductor die packageSANDISK CORP·Filed 2005·Granted Feb 16, 2010·2 cites·26 claims
- 3263US6449169B1Ball grid array package with interdigitated power ring and ground ringSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2001·Granted Sep 10, 2002·12 cites·10 claims
- 3362US8294251B2Stacked semiconductor package with localized cavities for wire bondingTAKIAR HEM·Filed 2008·Granted Oct 23, 2012·2 cites·20 claims
- 3462US7952179B2Semiconductor package having through holes for molding back side of packageSANDISK CORP·Filed 2007·Granted May 31, 2011·2 cites·16 claims
- 3560US7592699B2Hidden plating tracesSANDISK CORP·Filed 2005·Granted Sep 22, 2009·1 cites·18 claims
- 3658US7939382B2Method of fabricating a semiconductor package having through holes for molding back side of packageSANDISK CORP·Filed 2007·Granted May 10, 2011·1 cites·30 claims
- 3757US9006912B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2012·Granted Apr 14, 2015·0 cites·14 claims
- 3856US10051733B2Printed circuit board with coextensive electrical connectors and contact pad areasSANDISK TECHNOLOGIES INC·Filed 2015·Granted Aug 14, 2018·0 cites·18 claims
- 3956US6531762B1Semiconductor packageSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2001·Granted Mar 11, 2003·9 cites·11 claims
- 4053US8217522B2Printed circuit board with coextensive electrical connectors and contact pad areasLIAO CHIH-CHIN·Filed 2010·Granted Jul 10, 2012·0 cites·13 claims
- 4152US11031372B2Semiconductor device including dummy pull-down wire bondsWESTERN DIGITAL TECH INC·Filed 2019·Granted Jun 8, 2021·0 cites·24 claims
- 4252US9209159B2Hidden plating tracesTAKIAR HEM·Filed 2012·Granted Dec 8, 2015·0 cites·17 claims
- 4352US6740978B2Chip package capable of reducing moisture penetrationSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2003·Granted May 25, 2004·5 cites·10 claims
- 4451US11425817B2Side contact pads for high-speed memory cardWESTERN DIGITAL TECH INC·Filed 2020·Granted Aug 23, 2022·0 cites·18 claims
- 4550US8653653B2High density three dimensional semiconductor die packageYU CHEEMAN·Filed 2009·Granted Feb 18, 2014·0 cites·12 claims
- 4647US6465891B2Integrated-circuit package with a quick-to-count finger layout design on substrateSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2001·Granted Oct 15, 2002·4 cites·12 claims
- 4746US7772107B2Methods of forming a single layer substrate for high capacity memory cardsSANDISK CORP·Filed 2006·Granted Aug 10, 2010·0 cites·17 claims
- 4844US8637972B2Two-sided substrate lead connection for minimizing kerf width on a semiconductor substrate panelLIAO CHIH-CHIN·Filed 2007·Granted Jan 28, 2014·0 cites·30 claims
- 4944US6943439B2Substrate and fabrication method of the sameSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 2002·Granted Sep 13, 2005·1 cites·9 claims
- 5044US6391666B2Method for identifying defective elements in array molding of semiconductor packagingSILICONWARE PRECISION INDUSTRIES CO LTD·Filed 1999·Granted May 21, 2002·12 cites·5 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →