Inventor · disambiguated record
Chia-Pin Lin
Also filed as: LIN CHIA-PIN · LIN CHIA-PIN LINUS
90 granted patents·62 pending applications·347 citations·filing 2001–2025
99Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD120TAIWAN SEMICONDUCTOR MFG7LIN CHIA-PIN4LIM PENG-SOON2METAL IND RES & DEV CT2
Top patents by PatentIndex Score
152 records- 0198US11935781B2Integrated circuit structure with backside dielectric layer having air gapTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Mar 19, 2024·5 cites·20 claims
- 0298US11575047B2Semiconductor device active region profile and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 7, 2023·3 cites·20 claims
- 0397US12027626B2Semiconductor device active region profile and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 2, 2024·2 cites·20 claims
- 0497US11901236B2Semiconductor structure with gate-all-around devices and stacked FinFET devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Feb 13, 2024·2 cites·20 claims
- 0597US11444178B2Inner spacer linerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Sep 13, 2022·6 cites·20 claims
- 0697US11289584B2Inner spacer features for multi-gate transistorsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 29, 2022·8 cites·19 claims
- 0797US8362572B2Lower parasitic capacitance FinFETTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Jan 29, 2013·47 cites·7 claims
- 0897US8278173B2Method of fabricating gate structuresLIM PENG-SOON·Filed 2010·Granted Oct 2, 2012·34 cites·14 claims
- 0995US12080759B2Transistor source/drain regions and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 3, 2024·2 cites·20 claims
- 1095US12021133B2Inner spacer linerTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 25, 2024·2 cites·20 claims
- 1195US11973122B2Nano-FET semiconductor device and method of formingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Apr 30, 2024·2 cites·20 claims
- 1295US11631736B2Epitaxial source/drain feature with enlarged lower section interfacing with backside viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Apr 18, 2023·3 cites·20 claims
- 1395US11450559B2Integrated circuit structure with backside dielectric layer having air gapTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 20, 2022·3 cites·20 claims
- 1495US8759943B2Transistor having notched fin structure and method of making the sameTSENG CHIH-HUNG·Filed 2010·Granted Jun 24, 2014·48 cites·20 claims
- 1594US12087837B2Semiconductor device with backside contact and methods of forming suchTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Sep 10, 2024·2 cites·20 claims
- 1694US12015060B2Structure and formation method of semiconductor device with backside contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jun 18, 2024·2 cites·20 claims
- 1794US11417767B2Semiconductor devices including backside vias and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Aug 16, 2022·3 cites·20 claims
- 1894US8431453B2Plasma doping to reduce dielectric loss during removal of dummy layers in a gate structureHUANG YU-LIEN·Filed 2011·Granted Apr 30, 2013·23 cites·20 claims
- 1993US12426297B2Method and structure for air gap inner spacer in gate-all-around devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Sep 23, 2025·1 cites·20 claims
- 2093US8697539B2Method of making lower parasitic capacitance FinFETTAIWAN SEMICONDUCTOR MFG·Filed 2012·Granted Apr 15, 2014·14 cites·18 claims
- 2193US8609495B2Hybrid gate process for fabricating finfet deviceGAN TIAN-CHOY·Filed 2010·Granted Dec 17, 2013·38 cites·20 claims
- 2292US12040407B2Semiconductor devices including backside vias and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 16, 2024·1 cites·20 claims
- 2392US12015090B2Lightly-doped channel extensionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 18, 2024·1 cites·20 claims
- 2492US11489078B2Lightly-doped channel extensionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 1, 2022·2 cites·20 claims
- 2592US8937353B2Dual epitaxial process for a finFET deviceCHEN HUNG-KAI·Filed 2010·Granted Jan 20, 2015·23 cites·18 claims
- 2692US8575727B2Gate structuresTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 5, 2013·10 cites·14 claims
- 2792US2025366012A1Semiconductor device active region profile and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 2890US9312179B2Method of making a finFET, and finFET formed by the methodLIN CHIA-PIN·Filed 2010·Granted Apr 12, 2016·11 cites·20 claims
- 2989US11374128B2Method and structure for air gap inner spacer in gate-all-around devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 28, 2022·2 cites·20 claims
- 3088US12471306B2Semiconductor device active region profile and method of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Nov 11, 2025·0 cites·20 claims
- 3188US12363988B2Inner spacer features for multi-gate transistorsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jul 15, 2025·1 cites·20 claims
- 3288US8994116B2Hybrid gate process for fabricating FinFET deviceTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Mar 31, 2015·10 cites·20 claims
- 3388US2025311378A1Semiconductor structure with gate-all-around devices and stacked finfet devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3487US8034677B2Integrated method for forming high-k metal gate FinFET devicesTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Oct 11, 2011·9 cites·19 claims
- 3587US2025359207A1Epitaxial source/drain feature with enlarged lower section interfacing with backside viaTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3686US12382703B2Spacer features for nanosheet-based devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 5, 2025·1 cites·20 claims
- 3786US12369383B2Semiconductor structure with gate-all-around devices and stacked FinFET devicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 3886US2025359181A1Source and Drain Engineering Process for Multigate DevicesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3986US2025351483A1Transistor source/drain regionsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4085US12408377B2Semiconductor device structure with backside contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Sep 2, 2025·0 cites·20 claims
- 4184US12369334B2Method of manufacturing a semiconductor device and a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 4284US12308287B2Integrated circuit structure with backside dielectric layer having air gapTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted May 20, 2025·0 cites·20 claims
- 4384US12310057B2Semiconductor devices including backside vias and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted May 20, 2025·0 cites·20 claims
- 4484US12237230B2Semiconductor device with leakage current suppression and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 25, 2025·1 cites·20 claims
- 4584US12191379B2Multi-gate semiconductor device with inner spacer and fabrication method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 4684US2025318189A1Asymmetric Source/Drain for Backside Source ContactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 4783US12356662B2Asymmetric source/drain for backside source contactTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 8, 2025·0 cites·20 claims
- 4883US11515211B2Cut EPI process and structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 29, 2022·1 cites·20 claims
- 4983US2025344458A1Epitaxial FeaturesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 5083US2025318156A1Method of manufacturing a semiconductor device and a semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
Showing the top 50 of 152 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →