Inventor · disambiguated record
Chaiyasit Manovit
Also filed as: MANOVIT CHAIYASIT
8 granted patents·241 citations·filing 2002–2011
88Inventor score
Top patents by PatentIndex Score
8 records- 0195US7814378B2Verification of memory consistency and transactional memoryORACLE AMERICA INC·Filed 2007·Granted Oct 12, 2010·73 cites·20 claims
- 0290US6892286B2Shared memory multiprocessor memory model verification system and methodSUN MICROSYSTEMS INC·Filed 2002·Granted May 10, 2005·113 cites·31 claims
- 0387US7779393B1System and method for efficient verification of memory consistency model complianceORACLE AMERICA INC·Filed 2005·Granted Aug 17, 2010·20 cites·14 claims
- 0483US8219946B1Method for clock gating circuitsMANOVIT CHAIYASIT·Filed 2010·Granted Jul 10, 2012·11 cites·19 claims
- 0583US8099703B1Method and system for verifying power-optimized electronic designs using equivalency checkingMANOVIT CHAIYASIT·Filed 2008·Granted Jan 17, 2012·14 cites·22 claims
- 0671US8423935B1Method and apparatus for verifying output-based clock gatingMANOVIT CHAIYASIT·Filed 2011·Granted Apr 16, 2013·4 cites·20 claims
- 0762US7746116B1Method and apparatus to clock-gate a digital integrated circuit by use of feed-forward quiescent input analysisXILINX INC·Filed 2009·Granted Jun 29, 2010·5 cites·14 claims
- 0857US8898401B2Methods and apparatuses for improving speculation success in processorsMANOVIT CHAIYASIT·Filed 2008·Granted Nov 25, 2014·1 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →