Inventor · disambiguated record
Chanro Park
Also filed as: PARK CHANRO
315 granted patents·111 pending applications·2,136 citations·filing 2003–2024
99Inventor score
Top patents by PatentIndex Score
426 records- 0199US10418277B2Air gap spacer formation for nano-scale semiconductor devicesIBM·Filed 2018·Granted Sep 17, 2019·159 cites·20 claims
- 0299US9947804B1Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structureGLOBALFOUNDRIES INC·Filed 2017·Granted Apr 17, 2018·154 cites·14 claims
- 0399US9892961B1Air gap spacer formation for nano-scale semiconductor devicesIBM·Filed 2016·Granted Feb 13, 2018·49 cites·13 claims
- 0499US9847390B1Self-aligned wrap-around contacts for nanosheet devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Dec 19, 2017·74 cites·20 claims
- 0599US9780208B1Method and structure of forming self-aligned RMG gate for VFETGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·60 cites·19 claims
- 0699US9536793B1Self-aligned gate-first VFETs using a gate spacer recessGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 3, 2017·74 cites·13 claims
- 0799US9508604B1Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacersGLOBALFOUNDRIES INC·Filed 2016·Granted Nov 29, 2016·51 cites·25 claims
- 0899US9362181B1Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting productsGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 7, 2016·69 cites·31 claims
- 0998US11637179B2Airgap vertical transistor without structural collapseIBM·Filed 2020·Granted Apr 25, 2023·4 cites·17 claims
- 1098US11211452B1Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contactsIBM·Filed 2020·Granted Dec 28, 2021·7 cites·19 claims
- 1198US11211462B2Using selectively formed cap layers to form self-aligned contacts to source/drain regionsIBM·Filed 2020·Granted Dec 28, 2021·5 cites·16 claims
- 1298US11164793B2Reduced source/drain coupling for CFETIBM·Filed 2020·Granted Nov 2, 2021·6 cites·15 claims
- 1398US11024577B1Embedded anti-fuses for small scale applicationsIBM·Filed 2020·Granted Jun 1, 2021·8 cites·15 claims
- 1498US10903317B1Gate-all-around field effect transistors with robust inner spacers and methodsGLOBALFOUNDRIES US INC·Filed 2019·Granted Jan 26, 2021·24 cites·20 claims
- 1598US10529826B1Forming self-aligned gate and source/drain contacts using sacrificial gate cap spacer and resulting devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Jan 7, 2020·22 cites·20 claims
- 1698US10388770B1Gate and source/drain contact structures positioned above an active region of a transistor deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 20, 2019·36 cites·18 claims
- 1798US10243053B1Gate contact structure positioned above an active region of a transistor deviceGLOBALFOUNDRIES INC·Filed 2018·Granted Mar 26, 2019·33 cites·20 claims
- 1898US10103238B1Nanosheet field-effect transistor with full dielectric isolationGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 16, 2018·57 cites·20 claims
- 1998US9911619B1Fin cut with alternating two color fin hardmaskGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 6, 2018·24 cites·19 claims
- 2098US9899321B1Methods of forming a gate contact for a semiconductor device above the active regionGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 20, 2018·26 cites·25 claims
- 2198US9799748B1Method of forming inner spacers on a nano-sheet/wire deviceGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 24, 2017·33 cites·19 claims
- 2298US9780197B1Method of controlling VFET channel lengthGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 3, 2017·30 cites·20 claims
- 2398US9379017B1Method of forming a semiconductor structure including a plurality of fins and an alignment/overlay markGLOBALFOUNDRIES INC·Filed 2015·Granted Jun 28, 2016·32 cites·18 claims
- 2498US9178036B1Methods of forming transistor devices with different threshold voltages and the resulting productsGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 3, 2015·45 cites·29 claims
- 2597US11923246B2Via CD controllable top via structureIBM·Filed 2021·Granted Mar 5, 2024·4 cites·10 claims
- 2697US10679906B2Method of forming nanosheet transistor structures with reduced parasitic capacitance and improved junction sharpnessIBM·Filed 2018·Granted Jun 9, 2020·18 cites·15 claims
- 2797US10580692B1Integration of air spacer with self-aligned contact in transistorIBM·Filed 2018·Granted Mar 3, 2020·16 cites·20 claims
- 2897US10217846B1Vertical field effect transistor formation with critical dimension controlGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 26, 2019·21 cites·11 claims
- 2997US10211092B1Transistor with robust air spacerIBM·Filed 2018·Granted Feb 19, 2019·22 cites·20 claims
- 3097US9929048B1Middle of the line (MOL) contacts with two-dimensional self-alignmentGLOBALFOUNDRIES INC·Filed 2016·Granted Mar 27, 2018·22 cites·20 claims
- 3197US9818836B1Gate cut method for replacement metal gate integrationGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 14, 2017·24 cites·15 claims
- 3297US9761495B1Methods of performing concurrent fin and gate cut etch processes for FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2016·Granted Sep 12, 2017·24 cites·20 claims
- 3397US9691664B1Dual thick EG oxide integration under aggressive SG fin pitchGLOBALFOUNDRIES INC·Filed 2016·Granted Jun 27, 2017·22 cites·17 claims
- 3497US9337101B1Methods for selectively removing a fin when forming FinFET devicesGLOBALFOUNDRIES INC·Filed 2015·Granted May 10, 2016·25 cites·28 claims
- 3596US11881431B2Anti-fuse with laterally extended linerIBM·Filed 2021·Granted Jan 23, 2024·3 cites·16 claims
- 3696US11158544B2Vertical stacked nanosheet CMOS transistors with different work function metalsIBM·Filed 2019·Granted Oct 26, 2021·11 cites·20 claims
- 3796US10566248B1Work function metal patterning for N-P spaces between active nanostructures using unitary isolation pillarGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 18, 2020·16 cites·6 claims
- 3896US10410933B2Replacement metal gate patterning for nanosheet devicesGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 10, 2019·17 cites·18 claims
- 3996US10366930B1Self-aligned gate cut isolationGLOBALFOUNDRIES INC·Filed 2018·Granted Jul 30, 2019·15 cites·20 claims
- 4096US10115629B2Air gap spacer formation for nano-scale semiconductor devicesIBM·Filed 2017·Granted Oct 30, 2018·8 cites·8 claims
- 4196US9991131B1Dual mandrels to enable variable fin pitchGLOBALFOUNDRIES INC·Filed 2017·Granted Jun 5, 2018·18 cites·18 claims
- 4296US9966456B1Methods of forming gate electrodes on a vertical transistor deviceGLOBALFOUNDRIES INC·Filed 2016·Granted May 8, 2018·14 cites·20 claims
- 4396US9735242B2Semiconductor device with a gate contact positioned above the active regionGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 15, 2017·17 cites·13 claims
- 4496US9425106B1Methods of performing fin cut etch processes for taper FinFET semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 23, 2016·15 cites·20 claims
- 4596US9190488B1Methods of forming gate structure of semiconductor devices and the resulting devicesGLOBALFOUNDRIES INC·Filed 2014·Granted Nov 17, 2015·21 cites·13 claims
- 4695US12317514B2Resistive random-access memory structures with stacked transistorsIBM·Filed 2022·Granted May 27, 2025·1 cites·20 claims
- 4795US12046643B2Semiconductor structures with power rail disposed under active gateIBM·Filed 2021·Granted Jul 23, 2024·2 cites·25 claims
- 4895US11848384B2Semiconductor device with airgap spacer formation from backside of waferIBM·Filed 2021·Granted Dec 19, 2023·2 cites·20 claims
- 4995US11264481B2Self-aligned source and drain contactsIBM·Filed 2020·Granted Mar 1, 2022·3 cites·20 claims
- 5095US10373873B1Gate cut in replacement metal gate processGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 6, 2019·13 cites·15 claims
Showing the top 50 of 426 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →