Inventor · disambiguated record
Chao-Yuan Su
Also filed as: SU CHAO-YUAN
32 granted patents·15 pending applications·535 citations·filing 2001–2014
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG29SU CHAO-YUAN8UNITED MICROELECTRONICS CORP3HIMAX TECH LTD2CHAO TE-TSUNG1
Top patents by PatentIndex Score
47 records- 0197US6743660B2Method of making a wafer level chip scale packageTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jun 1, 2004·110 cites·20 claims
- 0294US7294937B2Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peelingTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Nov 13, 2007·26 cites·30 claims
- 0392US7825517B2Method for packaging semiconductor dies having through-silicon viasTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Nov 2, 2010·20 cites·11 claims
- 0490US7892962B2Nail-shaped pillar for wafer-level chip-scale packagingTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 22, 2011·20 cites·9 claims
- 0590US6636313B2Method of measuring photoresist and bump misalignmentTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Oct 21, 2003·37 cites·20 claims
- 0689US6756294B1Method for improving bump reliability for flip chip devicesTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jun 29, 2004·53 cites·26 claims
- 0788US7157734B2Semiconductor bond pad structures and methods of manufacturing thereofTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jan 2, 2007·23 cites·20 claims
- 0885US7709908B2High-voltage MOS transistor deviceUNITED MICROELECTRONICS CORP·Filed 2007·Granted May 4, 2010·14 cites·26 claims
- 0985US7126225B2Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peelingTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Oct 24, 2006·29 cites·14 claims
- 1078US7105920B2Substrate design to improve chip package reliabilityTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Sep 12, 2006·23 cites·18 claims
- 1178US6602775B1Method to improve reliability for flip-chip device for limiting pad designTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Aug 5, 2003·29 cites·25 claims
- 1277US7719076B2High-voltage MOS transistor deviceUNITED MICROELECTRONICS CORP·Filed 2007·Granted May 18, 2010·10 cites·27 claims
- 1376US8829653B2Exclusion zone for stress-sensitive circuit designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 9, 2014·2 cites·19 claims
- 1476US8624346B2Exclusion zone for stress-sensitive circuit designSU CHAO-YUAN·Filed 2006·Granted Jan 7, 2014·4 cites·23 claims
- 1574US8124458B2Method for packaging semiconductor dies having through-silicon viasSU CHAO-YUAN·Filed 2010·Granted Feb 28, 2012·3 cites·20 claims
- 1674US7256071B2Underfilling efficiency by modifying the substrate design of flip chipsTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 14, 2007·5 cites·14 claims
- 1774US6805279B2Fluxless bumping process using ionsTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Oct 19, 2004·28 cites·28 claims
- 1872US6715524B2DFR laminating and film removing systemTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Apr 6, 2004·16 cites·16 claims
- 1971US7468321B2Application of impressed-current cathodic protection to prevent metal corrosion and oxidationTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Dec 23, 2008·4 cites·20 claims
- 2069US7906425B2Fluxless bumping processTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Mar 15, 2011·4 cites·10 claims
- 2169US6770510B1Flip chip process of flux-less no-flow underfillTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Aug 3, 2004·13 cites·29 claims
- 2268US6974659B2Method of forming a solder ball using a thermally stable resinous protective layerTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Dec 13, 2005·15 cites·19 claims
- 2367US7134199B2Fluxless bumping processTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 14, 2006·10 cites·13 claims
- 2464US6821813B2Process for bonding solder bumps to a substrateTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 23, 2004·11 cites·20 claims
- 2561US7075016B2Underfilling efficiency by modifying the substrate design of flip chipsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jul 11, 2006·8 cites·16 claims
- 2659US9691749B2Exclusion zone for stress-sensitive circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Jun 27, 2017·0 cites·20 claims
- 2756US8497584B2Method to improve bump reliability for flip chip deviceCHEN YEN-MING·Filed 2004·Granted Jul 30, 2013·6 cites·9 claims
- 2854US7276454B2Application of impressed-current cathodic protection to prevent metal corrosion and oxidationTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Oct 2, 2007·5 cites·20 claims
- 2953US7154185B2Encapsulation method for SBGATAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Dec 26, 2006·6 cites·14 claims
- 3051US8629563B2Method for packaging semiconductor dies having through-silicon viasSU CHAO-YUAN·Filed 2012·Granted Jan 14, 2014·0 cites·20 claims
- 3149US6802250B2Stencil design for solder paste printingTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Oct 12, 2004·1 cites·15 claims
- 3244US2009111252A1Method for forming deep well region of high voltage deviceUNITED MICROELECTRONICS CORP·Filed 2007·Application pending·0 cites
- 3342US2008203566A1Stress buffer layer for packaging processSU CHAO-YUAN·Filed 2007·Application pending·0 cites
- 3441US7098082B2Microelectronics package assembly tool and method of manufacture therewithTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 29, 2006·0 cites·22 claims
- 3541US2007063347A1Packages, anisotropic conductive films, and conductive particles utilized thereinTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 3641US2006231960A1Non-cavity semiconductor packagesTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 3740US2015115361A1Lateral Diffused Metal Oxide SemiconductorHIMAX TECH LTD·Filed 2013·Application pending·0 cites
- 3839US2006076681A1Semiconductor package substrate for flip chip packagingTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 3939US2015115362A1Lateral Diffused Metal Oxide SemiconductorHIMAX TECH LTD·Filed 2014·Application pending·0 cites
- 4038US2006043556A1Stacked packaging methods and structuresSU CHAO-YUAN·Filed 2004·Application pending·0 cites
- 4138US2008246147A1Novel substrate design for semiconductor deviceSU CHAO-YUAN·Filed 2007·Application pending·0 cites
- 4238US2006073635A1Three dimensional package type stacking for thinner package applicationSU CHAO-YUAN·Filed 2004·Application pending·0 cites
- 4337US2006170114A1Novel method for copper wafer wire bondingSU CHAO-YUAN·Filed 2005·Application pending·0 cites
- 4437US2006109014A1Test pad and probe card for wafer acceptance testing and other applicationsCHAO TE-TSUNG·Filed 2004·Application pending·0 cites
- 4537US2006091535A1Fine pitch bonding pad layout and method of manufacturing sameTAIWAN SEMICONDUCTOR MFG·Filed 2004·Application pending·0 cites
- 4637US2004232560A1Flip chip assembly process and substrate used therewithFiled 2003·Application pending·0 cites
- 4734US2006065958A1Three dimensional package and packaging method for integrated circuitsTSAO PEI-HAW·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →