Inventor · disambiguated record
Chih Sieh Teng
Also filed as: TENG CHIH S · TENG CHIH SIEH
16 granted patents·3 pending applications·682 citations·filing 1988–2011
95Inventor score
Top patents by PatentIndex Score
19 records- 0194US7145191B1P-channel field-effect transistor with reduced junction capacitanceNAT SEMICONDUCTOR CORP·Filed 2004·Granted Dec 5, 2006·57 cites·58 claims
- 0294US4956311ADouble-diffused drain CMOS process using a counterdoping techniqueNAT SEMICONDUCTOR CORP·Filed 1989·Granted Sep 11, 1990·136 cites·18 claims
- 0393US7879669B1Fabrication of field-effect transistor with reduced junction capacitance and threshold voltage of magnitude that decreases with increasing channel lengthNAT SEMICONDUCTOR CORP·Filed 2006·Granted Feb 1, 2011·17 cites·40 claims
- 0491US6146958AMethods for making VLSI capacitors and high Q VLSI inductors using metal-filled via plugsNAT SEMICONDUCTOR CORP·Filed 1998·Granted Nov 14, 2000·112 cites·10 claims
- 0589US5761126ASingle-poly EPROM cell that utilizes a reduced programming voltage to program the cellNAT SEMICONDUCTOR CORP·Filed 1997·Granted Jun 2, 1998·71 cites·19 claims
- 0687US5908311AMethod for forming a mixed-signal CMOS circuit that includes non-volatile memory cellsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jun 1, 1999·58 cites·26 claims
- 0785US6797576B1Fabrication of p-channel field-effect transistor for reducing junction capacitanceNAT SEMICONDUCTOR CORP·Filed 2002·Granted Sep 28, 2004·35 cites·26 claims
- 0875US5943564ABiCMOS process for forming double-poly MOS and bipolar transistors with substantially identical device architecturesNAT SEMICONDUCTOR CORP·Filed 1996·Granted Aug 24, 1999·39 cites·17 claims
- 0974US5861647AVLSI capacitors and high Q VLSI inductors using metal-filled via plugsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Jan 19, 1999·41 cites·7 claims
- 1065US5399513ASalicide compatible CMOS process with a differential oxide implant maskNAT SEMICONDUCTOR CORP·Filed 1992·Granted Mar 21, 1995·29 cites·10 claims
- 1164US5605849AUse of oblique implantation in forming base of bipolar transistorNAT SEMICONDUCTOR CORP·Filed 1994·Granted Feb 25, 1997·20 cites·30 claims
- 1257US5733813AMethod for forming planarized field isolation regionsNAT SEMICONDUCTOR CORP·Filed 1996·Granted Mar 31, 1998·22 cites·10 claims
- 1353US2012181614A1Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction CapacitanceTENG CHIH SIEH·Filed 2011·Application pending·0 cites
- 1451US2012273880A1Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction CapacitanceTENG CHIH SIEH·Filed 2010·Application pending·0 cites
- 1551US2012181620A1Structure and Fabrication of Field-effect Transistor for Alleviating Short-channel Effects and/or Reducing Junction CapacitanceBULUCEA CONSTANTIN·Filed 2010·Application pending·0 cites
- 1647US5726069AUse of oblique implantation in forming emitter of bipolar transistorNAT SEMICONDUCTOR CORP·Filed 1994·Granted Mar 10, 1998·16 cites·40 claims
- 1742US5899723AOblique implantation in forming base of bipolar transistorNAT SEMICONDUCTOR CORP·Filed 1997·Granted May 4, 1999·8 cites·26 claims
- 1840US5607873AMethod for forming contact openings in a multi-layer structure that reduces overetching of the top conductive structureNAT SEMICONDUCTOR CORP·Filed 1996·Granted Mar 4, 1997·13 cites·19 claims
- 1935US4877751AMethod of forming an N+ poly-to- N+ silicon capacitor structure utilizing a deep phosphorous implantNAT SEMICONDUCTOR CORP·Filed 1988·Granted Oct 31, 1989·8 cites·24 claims
Join the waitlist — get patent alerts
Get an alert when Chih Sieh Teng files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →