Double-diffused drain CMOS process using a counterdoping technique

Abstract

The present process comprises the use of a blanket phosphorus (n-) implant coupled with a masked boron (P+) implant to permit the elimination of the conventional N+ implant and the LDD masks. The use of the blanket n- implant and the masked p+ implant allows production of an n- drain region which reduces hot-electron-induced degradation and a low concentration S/D region which is subsequently more easily counterdoped by a high concentration implant. A shallow blanket n+ implant is included prior to the P+ mask step to prevent contact resistance problems. Thereafter in the process of this invention, a salicide is formed at the sources and drains to produce a low sheet resistance in the contacts of the n-channel devices, notwithstanding the absence of the conventional thick n+ layer.

We claim: 
     
       1. A method of manufacturing a double-diffused drain CMOS device comprising the steps of: performing sequential low-energy blanket implants of n-type dopant of low and medium dosages into a substrate before and after formation of spacers adjacent to exposed edges of a plurality of gate structures;   performing a medium energy, high dosage implant of p-type dopant into p-channel regions of said substrate, said p-channel regions comprising areas exposed by a p+ mask, which also defines n-channel regions as regions not exposed by said p+ mask which previously received said blanket implants; and   forming a salicide in said p-channel and said n-channel regions by depositing a metal and exposing said substrate to temperature treatment.   
     
     
       2. A method as defined in claim 1 wherein said n-type dopant with which said low energy, low dosage blanket implant is performed prior to spacer formation is phosphorous, with dosage in the range of 9×10 13  to 4×10 14  atoms/cm 2  and energy in the range of 30 to 50 KeV. 
     
     
       3. A method as defined in claim 1 wherein said n-type dopant with which said low energy, medium dosage blanket implant is performed after spacer formation is arsenic, with dosage in the range of 5×10 14  to 9×10 14  atoms/cm 2  and energy in the range of 25 to 40 KeV. 
     
     
       4. A method as defined in claim 1 wherein said p-type dopant with which said high dosage, medium energy p+ implant is performed is BF 2 , with dosage in the range of 4×10 15  to 1×10 16  atoms/cm 2  and energy in the range of 45 to 60 KeV. 
     
     
       5. A method as defined in claim 1 wherein said metal used to form said salicide is titanium, thereby creating TiSi 2 . 
     
     
       6. A method as defined in claim wherein temperature treatment is performed after said p-type implant to anneal implant damage and activate said dopants. 
     
     
       7. A method as in claim 6 wherein said temperature treatment is rapid thermal annealing. 
     
     
       8. A method as defined in claim 1 wherein said spacers are formed of oxide and are of sufficient width to prevent gate to source/drain shorts when said salicide is formed. 
     
     
       9. A method as defined in claim 1 wherein said spacers are of appropriate width to minimize hot-electron effects. 
     
     
       10. In a method of manufacturing a double-diffused drain CMOS device comprising a semiconductor substrate containing one impurity type into which an implant of the opposite polarity type is performed through the exposed area of a composite mask to form a plurality of wells; removing the mask and performing an implant of the same polarity type as that in the substrate; defining a plurality of active regions within the n- and p-wells wherein the intended carrier charge of each active region is opposite in polarity to the well into which it is disposed; growing an isolating thermal oxide; performing a threshold voltage-determining implant and growing a gate oxide in the active regions; forming gate structures overlying portions of the active regions; forming contacts through a low temperature dielectric film deposited over the substrate by etching areas exposed by a contact mask; and forming a metal interconnect through which access to the device may be achieved; the improvement which comprises:   performing a low energy blanket implant of a low dosage of a first type of n-type dopant following the formation of doped polysilicon features;   forming spacers adjacent to exposed edges of said gate structures;   performing a low energy blanket implant of a medium dosage of a second type of n-type dopant;   performing a medium energy, high dosage implant of p-type dopant into p-channel regions exposed by a p+ mask; and   forming a salicide in the p-channel and n-channel active regions by depositing a metal and exposing said substrate to a siliciding temperature treatment.   
     
     
       11. The improvement as defined in claim 10 wherein said n-type dopant with which said low energy, low dosage blanket implant is performed prior to spacer formation is phosphorous, with dosage in the range of 9×10 13  to 4×10 14  atoms/cm 2  and energy in the range of 30 to 50 KeV. 
     
     
       12. The improvement as defined in claim 10 wherein said n-type dopant with which said low energy, medium dosage blanket implant is performed after spacer formation is arsenic, with dosage in the range of 5×10 14  to 9×10 14  atoms/cm 2  and energy in the range of 25 to 40 KeV. 
     
     
       13. The improvement as defined in claim 10 wherein said p-type dopant with which said high dosage, medium energy p+ implant is performed is BF 2 , with dosage in the range of 4×10 15  to 1×10 16  atoms/cm 2  and energy in the range of 45 to 60 KeV. 
     
     
       14. A method as defined in claim 10 wherein said metal used to form said salicide is titanium, thereby creating TiSi 2 . 
     
     
       15. The improvement as defined in claim 10 wherein temperature treatment is performed after said p-type implant to anneal implant damage and activate said dopants. 
     
     
       16. The improvement as in claim 15 wherein said temperature treatment is rapid thermal annealing. 
     
     
       17. The improvement as defined in claim 10 wherein said spacers are formed of oxide and are of sufficient width to prevent gate to source/drain shorts when said salicide is formed. 
     
     
       18. The improvement as defined in claim 10 wherein said spacers are of appropriate width to minimize hot-electron effects.