Inventor · disambiguated record
Charles H. Wallace
Also filed as: WALLACE CHARLES · WALLACE CHARLES H · WALLACE CHARLES HENRY
108 granted patents·100 pending applications·938 citations·filing 1974–2025
99Inventor score
Top patents by PatentIndex Score
208 records- 0198US9666451B2Self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted May 30, 2017·45 cites·25 claims
- 0298US7632610B2Sub-resolution assist featuresINTEL CORP·Filed 2004·Granted Dec 15, 2009·179 cites·20 claims
- 0397US9716037B2Gate aligned contact and method to fabricate sameGOLONZKA OLEG·Filed 2011·Granted Jul 25, 2017·65 cites·15 claims
- 0496US12266708B2Integrated circuit structures having dielectric anchor voidINTEL CORP·Filed 2023·Granted Apr 1, 2025·2 cites·25 claims
- 0596US10892223B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2016·Granted Jan 12, 2021·11 cites·25 claims
- 0696US9793163B2Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted Oct 17, 2017·28 cites·11 claims
- 0795US12218052B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2023·Granted Feb 4, 2025·1 cites·20 claims
- 0895US7569310B2Sub-resolution assist features for photolithography with trim endsINTEL CORP·Filed 2005·Granted Aug 4, 2009·168 cites·18 claims
- 0995US6479028B1Rapid synthesis of carbon nanotubes and carbon encapsulated metal nanoparticles by a displacement reactionUNIV CALIFORNIA·Filed 2000·Granted Nov 12, 2002·108 cites·17 claims
- 1094US10211088B2Self-aligned isotropic etch of pre-formed vias and plugs for back end of line (BEOL) interconnectsINTEL CORP·Filed 2015·Granted Feb 19, 2019·11 cites·20 claims
- 1193US10409152B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2017·Granted Sep 10, 2019·4 cites·20 claims
- 1293US9793159B2Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted Oct 17, 2017·13 cites·18 claims
- 1393US9005875B2Pre-patterned hard mask for ultrafast lithographic imagingINTEL CORP·Filed 2013·Granted Apr 14, 2015·12 cites·20 claims
- 1491US11854787B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2022·Granted Dec 26, 2023·1 cites·19 claims
- 1590US10559529B2Pitch division patterning approaches with increased overlay margin for back end of line (BEOL) interconnect fabrication and structures resulting therefromINTEL CORP·Filed 2016·Granted Feb 11, 2020·6 cites·26 claims
- 1690US10319625B2Metal via processing schemes with via critical dimension (CD) control for back end of line (BEOL) interconnects and the resulting structuresINTEL CORP·Filed 2015·Granted Jun 11, 2019·7 cites·20 claims
- 1789US7820550B2Negative tone double patterning methodINTEL CORP·Filed 2008·Granted Oct 26, 2010·10 cites·22 claims
- 1889US2024282633A1Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2024·Application pending·0 cites
- 1988US9558947B2Pattern decomposition lithography techniquesWALLACE CHARLES H·Filed 2011·Granted Jan 31, 2017·6 cites·16 claims
- 2088US2025125260A1Advanced lithography and self-assembled devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 2187US12033894B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2023·Granted Jul 9, 2024·0 cites·20 claims
- 2287US10490519B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2017·Granted Nov 26, 2019·2 cites·20 claims
- 2386US11145541B2Conductive via and metal line end fabrication and structures resulting therefromINTEL CORP·Filed 2017·Granted Oct 12, 2021·5 cites·18 claims
- 2486US7648803B2Diagonal corner-to-corner sub-resolution assist features for photolithographyINTEL CORP·Filed 2006·Granted Jan 19, 2010·10 cites·20 claims
- 2585US11373950B2Advanced lithography and self-assembled devicesINTEL CORP·Filed 2020·Granted Jun 28, 2022·1 cites·19 claims
- 2685US11107786B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2019·Granted Aug 31, 2021·2 cites·20 claims
- 2784US11756829B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 2884US7915171B2Double patterning techniques and structuresINTEL CORP·Filed 2008·Granted Mar 29, 2011·10 cites·20 claims
- 2983US10204830B2Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2017·Granted Feb 12, 2019·3 cites·20 claims
- 3081US7572557B2Non-collinear end-to-end structures with sub-resolution assist featuresINTEL CORP·Filed 2005·Granted Aug 11, 2009·6 cites·15 claims
- 3180US4256569AArrangement to improve the optimization of the value of finished cuts in a livestock processing plantITT·Filed 1979·Granted Mar 17, 1981·29 cites·28 claims
- 3279US10297467B2Self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2017·Granted May 21, 2019·2 cites·19 claims
- 3379US7521157B2Cross-shaped sub-resolution assist featureINTEL CORP·Filed 2006·Granted Apr 21, 2009·5 cites·19 claims
- 3479US2025351561A1Integrated circuit structures with backside gate cut or trench contact cutINTEL CORP·Filed 2025·Application pending·0 cites
- 3577US11495496B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2021·Granted Nov 8, 2022·0 cites·20 claims
- 3676US12278204B2Pattern decomposition lithography techniquesINTEL CORP·Filed 2021·Granted Apr 15, 2025·0 cites·15 claims
- 3776US11664274B2Method to repair edge placement errors in a semiconductor deviceINTEL CORP·Filed 2019·Granted May 30, 2023·2 cites·5 claims
- 3876US2025029915A1Vertical metal splitting using helmets and wrap-around dielectric spacersINTEL CORP·Filed 2024·Application pending·0 cites
- 3975US2025046713A1Self-aligned patterning with colored blocking and structures resulting therefromINTEL CORP·Filed 2024·Application pending·0 cites
- 4074US10910265B2Gate aligned contact and method to fabricate sameINTEL CORP·Filed 2020·Granted Feb 2, 2021·0 cites·20 claims
- 4173US12501659B2Integrated circuit structures having dielectric anchor voidINTEL CORP·Filed 2021·Granted Dec 16, 2025·0 cites·20 claims
- 4273US12249541B2Vertical edge blocking (VEB) technique for increasing patterning process marginINTEL CORP·Filed 2023·Granted Mar 11, 2025·0 cites·7 claims
- 4373US12080639B2Contact over active gate structures with metal oxide layers to inhibit shortingINTEL CORP·Filed 2019·Granted Sep 3, 2024·1 cites·17 claims
- 4473US2025254923A1Gate-all-around integrated circuit structures having depopulated channel structures using backside removal approachINTEL CORP·Filed 2025·Application pending·0 cites
- 4573US2024249946A1Gate spacing in integrated circuit structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 4672US11972979B21D vertical edge blocking (VEB) via and plugINTEL CORP·Filed 2023·Granted Apr 30, 2024·0 cites·22 claims
- 4772US7759028B2Sub-resolution assist featuresINTEL CORP·Filed 2009·Granted Jul 20, 2010·2 cites·22 claims
- 4872US4190100AInternal heat exchanger for meatITT·Filed 1978·Granted Feb 26, 1980·24 cites·24 claims
- 4972US2025227991A1Integrated circuit structures with backside gate partial cut or trench contact partial cutINTEL CORP·Filed 2025·Application pending·0 cites
- 5070US2024154037A1Integrated circuit structures having dielectric anchor and confined epitaxial source or drain structureINTEL CORP·Filed 2023·Application pending·0 cites
Showing the top 50 of 208 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →