Inventor · disambiguated record
Cheng Wang
Also filed as: WANG CHENG · WANG CHENG C · WANG CHENG-CHOU
54 granted patents·9 pending applications·391 citations·filing 2005–2023
98Inventor score
Top patents by PatentIndex Score
63 records- 0197US8001421B2Compiler technique for efficient register checkpointing to support transaction roll-backINTEL CORP·Filed 2010·Granted Aug 16, 2011·73 cites·20 claims
- 0293US9146844B2Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic regionINTEL CORP·Filed 2013·Granted Sep 29, 2015·17 cites·22 claims
- 0393US8683243B2Dynamic core selection for heterogeneous multi-core systemsWU YOUFENG·Filed 2011·Granted Mar 25, 2014·20 cites·29 claims
- 0491US8549504B2Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic regionBRETERNITZ JR MAURICIO·Filed 2010·Granted Oct 1, 2013·19 cites·23 claims
- 0591US7506217B2Apparatus and method for software-based control flow checking for soft error detection to improve microprocessor reliabilityINTEL CORP·Filed 2005·Granted Mar 17, 2009·28 cites·9 claims
- 0690US7757221B2Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraintsINTEL CORP·Filed 2005·Granted Jul 13, 2010·28 cites·17 claims
- 0788US9817644B2Apparatus, method, and system for providing a decision mechanism for conditional commits in an atomic regionINTEL CORP·Filed 2015·Granted Nov 14, 2017·5 cites·20 claims
- 0888US9710280B2Overlapping atomic regions in a processorCHUNG JAEWOONG·Filed 2011·Granted Jul 18, 2017·11 cites·20 claims
- 0987US9501135B2Dynamic core selection for heterogeneous multi-core systemsINTEL CORP·Filed 2014·Granted Nov 22, 2016·6 cites·20 claims
- 1086US7865885B2Using transactional memory for precise exception handling in aggressive dynamic binary optimizationsINTEL CORP·Filed 2006·Granted Jan 4, 2011·18 cites·17 claims
- 1184US9152417B2Expediting execution time memory aliasing checkingWANG CHENG·Filed 2011·Granted Oct 6, 2015·9 cites·25 claims
- 1284US8132158B2Mechanism for software transactional memory commit/abort in unmanaged runtime environmentWANG CHENG·Filed 2006·Granted Mar 6, 2012·14 cites·24 claims
- 1383US8935678B2Methods and apparatus to form a resilient objective instruction constructWU YOUFENG·Filed 2012·Granted Jan 13, 2015·7 cites·20 claims
- 1482US8296749B2Program translation and transactional memory formationZHAO CHENGYAN·Filed 2007·Granted Oct 23, 2012·15 cites·18 claims
- 1582US7802136B2Compiler technique for efficient register checkpointing to support transaction roll-backINTEL CORP·Filed 2006·Granted Sep 21, 2010·11 cites·17 claims
- 1680US10268497B2Conjugate code generation for efficient dynamic optimizationsINTEL CORP·Filed 2013·Granted Apr 23, 2019·6 cites·22 claims
- 1780US8060482B2Efficient and consistent software transactional memoryWANG CHENG·Filed 2006·Granted Nov 15, 2011·9 cites·27 claims
- 1879US10489158B2Processors, methods, systems, and instructions to selectively fence only persistent storage of given data relative to subsequent storesINTEL CORP·Filed 2014·Granted Nov 26, 2019·5 cites·23 claims
- 1978US11755099B2Dynamic core selection for heterogeneous multi-core systemsINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 2078US7844946B2Methods and apparatus to form a transactional objective instruction construct from lock-based critical sectionsINTEL CORP·Filed 2006·Granted Nov 30, 2010·9 cites·28 claims
- 2178US7694281B2Two-pass MRET trace selection for dynamic optimizationINTEL CORP·Filed 2005·Granted Apr 6, 2010·10 cites·15 claims
- 2276US9715388B2Instruction and logic to monitor loop trip count and remove loop optimizationsCHUNG JAEWOONG·Filed 2012·Granted Jul 25, 2017·4 cites·26 claims
- 2376US8522223B2Automatic function call in multithreaded applicationWANG CHENG·Filed 2006·Granted Aug 27, 2013·8 cites·11 claims
- 2474US10534424B2Dynamic core selection for heterogeneous multi-core systemsINTEL CORP·Filed 2016·Granted Jan 14, 2020·1 cites·24 claims
- 2574US10437319B2Dynamic core selection for heterogeneous multi-core systemsINTEL CORP·Filed 2016·Granted Oct 8, 2019·1 cites·10 claims
- 2673US9715376B2Energy/performance with optimal communication in dynamic parallelization of single threaded programsWANG CHENG·Filed 2008·Granted Jul 25, 2017·6 cites·18 claims
- 2773US8418156B2Two-stage commit (TSC) region for dynamic binary optimization in X86WANG CHENG·Filed 2009·Granted Apr 9, 2013·6 cites·18 claims
- 2873US7937621B2Transient fault detection by integrating an SRMT code and a non SRMT code in a single applicationINTEL CORP·Filed 2007·Granted May 3, 2011·6 cites·17 claims
- 2971US9940229B2Technologies for persistent memory programmingINTEL CORP·Filed 2014·Granted Apr 10, 2018·3 cites·24 claims
- 3071US9690582B2Instruction and logic for cache-based speculative vectorizationVASUDEVAN NALINI·Filed 2013·Granted Jun 27, 2017·4 cites·20 claims
- 3170US8706982B2Mechanisms for strong atomicity in a transactional memory systemSAHA BRATIN·Filed 2007·Granted Apr 22, 2014·5 cites·9 claims
- 3268US9292221B2Bi-directional copying of register content into shadow registersWANG CHENG·Filed 2011·Granted Mar 22, 2016·2 cites·23 claims
- 3367US9405547B2Register allocation for rotation based alias protection registerWANG CHENG·Filed 2011·Granted Aug 2, 2016·2 cites·16 claims
- 3466US9836316B2Flexible acceleration of code executionINTEL CORP·Filed 2012·Granted Dec 5, 2017·2 cites·25 claims
- 3566US7818744B2Apparatus and method for redundant software thread computationINTEL CORP·Filed 2005·Granted Oct 19, 2010·3 cites·15 claims
- 3666US2019332158A1Dynamic core selection for heterogeneous multi-core systemsINTEL CORP·Filed 2019·Application pending·0 cites
- 3765US9710279B2Method and apparatus for speculative vectorizationINTEL CORP·Filed 2014·Granted Jul 18, 2017·1 cites·22 claims
- 3864US10324768B2Lightweight restricted transactional memory for speculative compiler optimizationINTEL CORP·Filed 2014·Granted Jun 18, 2019·1 cites·21 claims
- 3964US10303525B2Systems, apparatuses, and methods for data speculation executionINTEL CORP·Filed 2014·Granted May 28, 2019·1 cites·19 claims
- 4064US9690552B2Technologies for low-level composable high performance computing librariesINTEL CORP·Filed 2014·Granted Jun 27, 2017·1 cites·25 claims
- 4164US8443343B2Context-sensitive slicing for dynamically parallelizing binary programsBLOMSTEDT JOSEPH·Filed 2009·Granted May 14, 2013·6 cites·19 claims
- 4263US9519467B2Efficient and consistent software transactional memoryWANG CHENG·Filed 2011·Granted Dec 13, 2016·1 cites·12 claims
- 4362US9542211B2Co-designed dynamic language accelerator for a processorINTEL CORP·Filed 2014·Granted Jan 10, 2017·1 cites·15 claims
- 4462US9495168B2Allocation of alias registers in a pipelined scheduleINTEL CORP·Filed 2013·Granted Nov 15, 2016·1 cites·19 claims
- 4559US10437318B2Dynamic core selection for heterogeneous multi-core systemsINTEL CORP·Filed 2016·Granted Oct 8, 2019·0 cites·19 claims
- 4658US8156480B2Methods and apparatus to form a resilient objective instruction constructWU YOUFENG·Filed 2006·Granted Apr 10, 2012·1 cites·30 claims
- 4758US7937620B2Transient fault detection by integrating an SRMT code and a non SRMT code in a single applicationINTEL CORP·Filed 2007·Granted May 3, 2011·1 cites·17 claims
- 4856US8332558B2Compact trace trees for dynamic binary parallelizationPORTO JOAO PAULO·Filed 2008·Granted Dec 11, 2012·3 cites·20 claims
- 4954US9971703B2Technologies for position-independent persistent memory pointersINTEL CORP·Filed 2017·Granted May 15, 2018·0 cites·20 claims
- 5054US9588814B2Fast approximate conflict detectionINTEL CORP·Filed 2014·Granted Mar 7, 2017·0 cites·25 claims
Showing the top 50 of 63 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →