Inventor · disambiguated record
Chih-Hsiang Yao
Also filed as: YAO CHIH-HSIANG
35 granted patents·7 pending applications·451 citations·filing 2002–2025
97Inventor score
Files withTAIWAN SEMICONDUCTOR MFG25TAIWAN SEMICONDUCTOR MFG CO LTD11YAO CHIH-HSIANG2CHI MIN-HWA1KUO CHENG-CHENG1
Top patents by PatentIndex Score
42 records- 0199US8836141B2Conductor layout technique to reduce stress-induced void formationsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Sep 16, 2014·105 cites·13 claims
- 0291US7791070B2Semiconductor device fault detection system and methodTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Sep 7, 2010·25 cites·20 claims
- 0390US7592710B2Bond pad structure for wire bondingTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Sep 22, 2009·19 cites·20 claims
- 0490US7253531B1Semiconductor bonding pad structureTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 7, 2007·23 cites·20 claims
- 0590US7098077B2Semiconductor chip singulation methodTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 29, 2006·50 cites·19 claims
- 0689US7880303B2Stacked contact with low aspect ratioTAIWAN SEMICONDUCTOR MFG·Filed 2007·Granted Feb 1, 2011·16 cites·19 claims
- 0788US9477803B2Method of generating techfile having reduced corner variation valueTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Oct 25, 2016·9 cites·20 claims
- 0883US7741714B2Bond pad structure with stress-buffering layer capping interconnection metal layerTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jun 22, 2010·36 cites·32 claims
- 0982US9793212B2Interconnect structures and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Oct 17, 2017·4 cites·20 claims
- 1082US9209079B2Conductor layout technique to reduce stress-induced void formationsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Dec 8, 2015·4 cites·13 claims
- 1180US7081679B2Structure and method for reinforcing a bond pad on a chipTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jul 25, 2006·29 cites·20 claims
- 1278US6927498B2Bond pad for flip chip packageTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Aug 9, 2005·23 cites·32 claims
- 1375US7265436B2Non-repeated and non-uniform width seal ring structureTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Sep 4, 2007·23 cites·18 claims
- 1474US2025343077A1Modifying tsv layout and the structures thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 1572US6864701B2Test patterns for measurement of effective vacancy diffusion areaTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Mar 8, 2005·12 cites·25 claims
- 1671US6831365B1Method and pattern for reducing interconnect failuresTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Dec 14, 2004·18 cites·17 claims
- 1770US7042097B2Structure for reducing stress-induced voiding in an interconnect of integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted May 9, 2006·14 cites·20 claims
- 1869US2025046655A1Modifying tsv layout and the structures thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 1963US8669661B2Metal line and via formation using hard masksYAO CHIH-HSIANG·Filed 2012·Granted Mar 11, 2014·2 cites·19 claims
- 2063US7244673B2Integration film scheme for copper / low-k interconnectTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Jul 17, 2007·12 cites·59 claims
- 2161US2025192027A1Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 2260US10872806B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 22, 2020·0 cites·20 claims
- 2357US6787803B1Test patterns for measurement of low-k dielectric cracking thresholdsTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Sep 7, 2004·5 cites·29 claims
- 2456US10170355B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 2556US6812069B2Method for improving semiconductor process wafer CMP uniformity while avoiding fractureTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Nov 2, 2004·5 cites·19 claims
- 2655US7777338B2Seal ring structure for integrated circuit chipsTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 17, 2010·6 cites·50 claims
- 2755US6787484B2Method of reducing visible light induced arcing in a semiconductor wafer manufacturing processTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Sep 7, 2004·6 cites·20 claims
- 2854US9711391B1Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jul 18, 2017·0 cites·20 claims
- 2953US10169506B2Circuit design method and systemTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 1, 2019·0 cites·20 claims
- 3052US9437485B2Method for line stress reduction through dummy shoulder structuresTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Sep 6, 2016·0 cites·20 claims
- 3150US8435802B2Conductor layout technique to reduce stress-induced void formationsCHI MIN-HWA·Filed 2006·Granted May 7, 2013·0 cites·11 claims
- 3249US6759342B2Method of avoiding dielectric arcingTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jul 6, 2004·4 cites·18 claims
- 3348US7074629B2Test patterns for measurement of effective vacancy diffusion areaTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Jul 11, 2006·1 cites·20 claims
- 3447US8450200B2Method for stacked contact with low aspect ratioYU CHEN-HUA·Filed 2010·Granted May 28, 2013·0 cites·20 claims
- 3545US7470994B2Bonding pad structure and method for making the sameTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Dec 30, 2008·0 cites·11 claims
- 3644US7772701B2Integrated circuit having improved interconnect structureTAIWAN SEMICONDUCTOR MFG·Filed 2006·Granted Aug 10, 2010·0 cites·21 claims
- 3743US2006055002A1Methods for enhancing die saw and packaging reliabilityTAIWAN SEMICONDUCTOR MFG·Filed 2005·Application pending·0 cites
- 3842US8692351B2Dummy shoulder structure for line stress reductionKUO CHENG CHENG·Filed 2010·Granted Apr 8, 2014·0 cites·20 claims
- 3940US7151052B2Multiple etch-stop layer deposition scheme and materialsTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Dec 19, 2006·0 cites·7 claims
- 4040US2006108696A1Structure for reducing stress-induced voiding in an interconnect of integrated circuitsYAO CHIH-HSIANG·Filed 2006·Application pending·0 cites
- 4137US2005133241A1Chip orientation and attachment methodTAIWAN SEMICONDUCTOR MFG·Filed 2003·Application pending·0 cites
- 4237US2004251549A1Hybrid copper/low k dielectric interconnect integration method and deviceFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →