Structure for reducing stress-induced voiding in an interconnect of integrated circuits
Abstract
A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, the interconnect having a first portion and at least a second portion narrower than the first portion. The structure comprises at least one interior slot disposed in the first portion in proximity to the intersection of the first portion and the second portion. The present invention also includes methods of making the interconnect and the structure. A conductive interconnect structure comprises a first portion and at least a second portion narrower than the first portion; and a stress reducing structure comprising a transition portion formed at an intersection of the first portion and the second portion.
Claims
exact text as granted — not AI-modified1 . A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, said interconnect having a first portion and at least one second portion narrower than said first portion, said structure comprising:
at least one interior slot disposed in the first portion in proximity to an intersection of said first portion and said second portion.
2 . The structure of claim 1 , wherein said first and second interconnect portions converge at said intersection, said intersection comprising a plane at a transition from said first interconnect portion to the second interconnect potion.
3 . The structure of claim 1 , wherein said structure further comprises an electrical connection between the first and second interconnect portions.
4 . The structure of claim 1 , wherein said slot is longer than a width of said intersection.
5 . The structure of claim 1 , wherein said first portion and said second portion comprise copper.
6 . (canceled)
7 . A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, comprising:
a first interconnect portion and at least one second interconnect portion narrower than said first interconnect portion; said first and second interconnect portions being connected at an intersection; and said second interconnect portion being connected to a via; wherein the first interconnect portion has at least one interior slot disposed portion in proximity to said intersection of said first and second interconnect portions, said interior slot having a length that is greater than a width of said intersection.
8 . The structure of claim 7 , wherein said intersection comprises a plane at a transition from said first interconnect portion to said second interconnect potion.
9 . The structure of claim 8 , wherein said intersection comprises an electrical connection between said first and second interconnect portions.
10 . The structure of claim 7 , wherein said interior slot has a length and a width, the length and width being unequal.
11 . The structure of claim 10 , wherein said interior slot is oriented approximately parallel to said intersection.
12 . The structure of claim 7 , wherein said interior slot has an elongated shape, said interior slot being oriented approximately parallel to said intersection.
13 . The structure of claim 12 , wherein a shortest distance from said interior slot to said intersection is smaller than 100 times of a critical dimension.
14 . The structure of claim 12 , wherein a shortest distance from said slot to said intersection is smaller than one half of a length of said first portion.
15 . A structure for reducing stress-induced voiding in an interconnect of an integrated circuit, comprising:
a first interconnect portion and at least one second interconnect portion narrower than said first interconnect portion; wherein said first interconnect portion comprises first and second elongated interior slots disposed adjacent to an intersection of said first and second interconnect portions, said first and second slots each having a longitudinal axis that is oriented approximately perpendicular to a plane of said intersection.
16 . The structure of claim 15 , wherein a shortest distance between said first and second slots is smaller than 10 times of a critical dimension, and wherein said shortest distance is greater than a width of said first interconnect portion.
17 . The structure of claim 16 , wherein a shortest distance from said first slot to said intersection is smaller than 100 times of said critical dimension.
18 . The structure of claim 16 , wherein a shortest distance from said first slot to said intersection is smaller than one half of a length of said first interconnect portion.
19 - 27 . (canceled)
28 . The structure of claim 14 , wherein said structure comprises an electrical connection between said first and second interconnect portions.
29 . The structure of claim 14 , wherein said second interconnect portion is connected to a via.
30 . The structure of claim 14 , wherein said first and second interconnect portions comprise copper.Join the waitlist — get patent alerts
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