Inventor · disambiguated record
Colin Eddy
Also filed as: EDDY COLIN
75 granted patents·3 pending applications·228 citations·filing 2008–2020
98Inventor score
Top patents by PatentIndex Score
78 records- 0196US9811468B2Set associative cache memory with heterogeneous replacement policyVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Nov 7, 2017·43 cites·15 claims
- 0295US9760496B2Simultaneous invalidation of all address translation cache entries associated with an X86 process context identifierVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Sep 12, 2017·24 cites·20 claims
- 0390US8782348B2Microprocessor cache line evict arrayEDDY COLIN·Filed 2008·Granted Jul 15, 2014·27 cites·39 claims
- 0490US8392693B2Fast REP STOS using grabline operationsHENRY G GLENN·Filed 2010·Granted Mar 5, 2013·13 cites·34 claims
- 0589US11467972B2L1D to L2 evictionCENTAUR TECH INC·Filed 2020·Granted Oct 11, 2022·2 cites·20 claims
- 0688US9842055B2Address translation cache that supports simultaneous invalidation of common context entriesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Dec 12, 2017·12 cites·20 claims
- 0787US9569363B2Selective prefetching of physically sequential cache line to cache line that includes loaded page table entryVIA TECH INC·Filed 2015·Granted Feb 14, 2017·5 cites·21 claims
- 0887US9244686B2Microprocessor that translates conditional load/store instructions into variable number of microinstructionsHENRY G GLENN·Filed 2012·Granted Jan 26, 2016·10 cites·47 claims
- 0986US8533437B2Guaranteed prefetch instructionHENRY G GLENN·Filed 2010·Granted Sep 10, 2013·9 cites·29 claims
- 1082US8234450B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2010·Granted Jul 31, 2012·6 cites·8 claims
- 1181US9501286B2Microprocessor with ALU integrated into load unitCOL GERARD M·Filed 2009·Granted Nov 22, 2016·9 cites·38 claims
- 1280US9898418B2Processor including single invalidate page instructionVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Feb 20, 2018·3 cites·17 claims
- 1380US9652398B2Cache replacement policy that considers memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted May 16, 2017·5 cites·18 claims
- 1480US8533438B2Store-to-load forwarding based on load/store address computation source information comparisonsHOOKER RODNEY E·Filed 2010·Granted Sep 10, 2013·6 cites·24 claims
- 1579US8433853B2Prefetching of next physically sequential cache line after cache line that includes loaded page table entryEDDY COLIN·Filed 2012·Granted Apr 30, 2013·4 cites·20 claims
- 1678US9817764B2Multiple data prefetchers that defer to one another based on prefetch effectiveness by memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Nov 14, 2017·4 cites·21 claims
- 1778US7827390B2Microprocessor with private microcode RAMVIA TECH INC·Filed 2008·Granted Nov 2, 2010·8 cites·29 claims
- 1875US8161246B2Prefetching of next physically sequential cache line after cache line that includes loaded page table entryHOOKER RODNEY E·Filed 2009·Granted Apr 17, 2012·5 cites·11 claims
- 1974US10114794B2Programmable load replay precluding mechanismVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Oct 30, 2018·3 cites·12 claims
- 2074US9542332B2System and method for performing hardware prefetch tablewalks having lowest tablewalk priorityVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Jan 10, 2017·3 cites·20 claims
- 2172US7996650B2Microprocessor that performs speculative tablewalksVIA TECH INC·Filed 2008·Granted Aug 9, 2011·5 cites·23 claims
- 2270US10387318B2Prefetching with level of aggressiveness based on effectiveness by memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Aug 20, 2019·2 cites·25 claims
- 2370US9910785B2Cache memory budgeted by ways based on memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Mar 6, 2018·2 cites·17 claims
- 2470US9652400B2Fully associative cache memory budgeted by memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted May 16, 2017·2 cites·21 claims
- 2570US8489823B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2012·Granted Jul 16, 2013·2 cites·10 claims
- 2668US9378019B2Conditional load instructions in an out-of-order execution microprocessorHENRY G GLENN·Filed 2012·Granted Jun 28, 2016·2 cites·39 claims
- 2767US8566565B2Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applicationsHOOKER RODNEY E·Filed 2008·Granted Oct 22, 2013·3 cites·55 claims
- 2867US8301842B2Efficient pseudo-LRU for colliding accessesEDDY COLIN·Filed 2010·Granted Oct 30, 2012·2 cites·20 claims
- 2965US10127046B2Mechanism to preclude uncacheable-dependent load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Nov 13, 2018·1 cites·12 claims
- 3064US9898411B2Cache memory budgeted by chunks based on memory access typeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Feb 20, 2018·1 cites·16 claims
- 3163US8543765B2Efficient data prefetching in the presence of load hitsGLOVER CLINTON THOMAS·Filed 2012·Granted Sep 24, 2013·1 cites·16 claims
- 3262US9645822B2Conditional store instructions in an out-of-order execution microprocessorHENRY G GLENN·Filed 2012·Granted May 9, 2017·1 cites·43 claims
- 3362US8291172B2Multi-modal data prefetcherHOOKER RODNEY E·Filed 2010·Granted Oct 16, 2012·1 cites·37 claims
- 3458US9798669B1System and method of determining memory ownership on cache line basis for detecting self-modifying codeVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 24, 2017·0 cites·21 claims
- 3558US9798670B1System and method of determining memory ownership on cache line basis for detecting self-modifying code including modification of a cache line with an executing instructionVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 24, 2017·0 cites·20 claims
- 3658US9798675B1System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with looping instructionsVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 24, 2017·0 cites·22 claims
- 3758US9792216B1System and method of determining memory ownership on cache line basis for detecting self-modifying code including code with instruction that overlaps cache line boundariesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2016·Granted Oct 17, 2017·0 cites·21 claims
- 3858US9703359B2Power saving mechanism to reduce load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Jul 11, 2017·0 cites·21 claims
- 3956US11314657B1Tablewalk takeoverCENTAUR TECH INC·Filed 2020·Granted Apr 26, 2022·0 cites·20 claims
- 4056US9727480B2Efficient address translation caching in a processor that supports a large number of different address spacesVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Aug 8, 2017·0 cites·20 claims
- 4156US8539209B2Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operationPOGOR BRYAN WAYNE·Filed 2009·Granted Sep 17, 2013·2 cites·23 claims
- 4255US9952875B2Microprocessor with ALU integrated into store unitCOL GERARD M·Filed 2009·Granted Apr 24, 2018·0 cites·38 claims
- 4354US10108430B2Mechanism to preclude load replays dependent on off-die control element access in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Oct 23, 2018·0 cites·13 claims
- 4454US2014013058A1Prefetching of next physically sequential cache line after cache line that includes loaded page table entryVIA TECH INC·Filed 2013·Application pending·0 cites
- 4553US9915998B2Power saving mechanism to reduce load replays in out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2015·Granted Mar 13, 2018·0 cites·21 claims
- 4652US9740271B2Apparatus and method to preclude X86 special bus cycle load replays in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted Aug 22, 2017·0 cites·21 claims
- 4752US9645827B2Mechanism to preclude load replays dependent on page walks in an out-of-order processorVIA ALLIANCE SEMICONDUCTOR CO LTD·Filed 2014·Granted May 9, 2017·0 cites·21 claims
- 4852US8392666B2Low power high speed load-store collision detectorHOOKER RODNEY E·Filed 2009·Granted Mar 5, 2013·0 cites·21 claims
- 4951US8108624B2Data cache with modified bit arrayHOOKER RODNEY E·Filed 2009·Granted Jan 31, 2012·0 cites·33 claims
- 5051US8108621B2Data cache with modified bit arrayHOOKER RODNEY E·Filed 2009·Granted Jan 31, 2012·0 cites·39 claims
Showing the top 50 of 78 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →